A Charge Pump Based Power Management Unit With 66%-Efficiency in 65 nm CMOS

Mahmoud, Abdulqader; Alhawari, Mohammad; Mohammad, Baker; Saleh, Hani; Ismail, Mohammed

doi:10.1109/iscas.2018.8350898

Cited by 12 publications

(11 citation statements)

References 12 publications

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“…In addition, the proposed HVG has the highest pumping efficiency of 88~90% compared to other research studies [14,19,[21][22][23]. In this study, the obtained frequency of 11.2 MHz makes the proposed design superior to those reported in [14,19,[21][22][23][24][25] and adequate for the proposed HVG performance to be compatible with the RFID transponder EEPROM. As the aim of this research was to reduce the power dissipation and the ripple voltage, so it is obvious from Table 1 that the proposed HVG achieved the desired results that were compatible with the RFID transponder EEPROM.…”

Section: Resultsmentioning

confidence: 69%

“…Moreover, the use of pass transistors reduced the voltage loss problems and the reversed charge-sharing problem in the proposed CP circuit. As a result, the overall high-voltage generation process was boosted compared to other research studies [14,[18][19][20][21][22][23][24][25]. Conversely, the use of the NMOS switch between the CP circuit and the voltage regulator reduced the output ripple voltage of the proposed HVG.…”

Section: Resultsmentioning

confidence: 82%

“…To check the impact of the transistor mismatch during the design, a Monte Carlo simulation was performed with 100 runs for this proposed design, as shown in Fig 12. In addition, this evaluation is able to provide a process variation mismatch. Table 1 illustrates the performance comparison of the proposed HVG with other recently published research studies [14,[18][19][20][21][22][23][24][25]. Most of the previous research studies have used diodeconnected configurations to design the CP circuit, which is the most power-hungry module in HVG [14, 18-19, 21, 23, 25].…”

Section: Resultsmentioning

confidence: 99%

“…In the HVG, the maximum amount of power was consumed by the CP circuit, as this circuit was utilized to boost up the supply voltage. Therefore, in this research, an eightstage modified CTS-based CP circuit was proposed which employed triple well NMOS CTSs rather than diode-configured switches [14,[24][25]. In addition, no substrate current was formed throughout the dynamic control process, as all the PMOS transistors were removed from each stage of this proposed design.…”

Section: Resultsmentioning

confidence: 99%

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A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM

et al. 2020

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A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID-EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non-overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only-119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm 2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.

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Section: Resultsmentioning

confidence: 69%

Section: Resultsmentioning

confidence: 82%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

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A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM

et al. 2020

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“…Charge pumps have been traditionally adopted in nonvolatile memories and SRAMs, in which the design is driven by settling time and low area, or RF antenna switch controllers and LCD drivers, where the main design constraint is the current drivability [9][10][11]. More recently, CPs are widely used to adapt the voltage levels between two or more functional blocks and to convey the electric energy, and, more recently, IoT nodes [1][2][3][4][12][13][14][15][16][17][18][19][20][21][22][23]. In this latter context, the design of a PMIC based on CPs is a challenging task since it must fulfill a very low input voltage supply (few hundreds of millivolts and high-power conversion efficiency).…”

Section: Introductionmentioning

confidence: 99%

A Review of Charge Pump Topologies for the Power Management of IoT Nodes

2019

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With the aim of providing designer guidelines for choosing the most suitable solution, according to the given design specifications, in this paper a review of charge pump (CP) topologies for the power management of Internet of Things (IoT) nodes is presented. Power management of IoT nodes represents a challenging task, especially when the output of the energy harvester is in the order of few hundreds of millivolts. In these applications, the power management section can be profitably implemented, exploiting CPs. Indeed, presently, many different CP topologies have been presented in literature. Finally, a data-driven comparison is also provided, allowing for quantitative insight into the state-of-the-art of integrated CPs.

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