A charge transfer-based high performance, ultra-low power PLL charge pump

Schober, Susan; Choma, J.

doi:10.1109/lascas.2015.7250412

Cited by 4 publications

(2 citation statements)

References 5 publications

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“…IP and IN in Fig. 2) and adopting a switched capacitor approach to transferring charge to and from the LF capacitance [9]. Minimum-sized transistor switches-as opposed to large transistors used for the current mirrors with conventional analog control switches-and a relatively small wire interconnect capacitor in the proposed CP allow for much less power consumption with a compact active area as compared to the state of the art CP.…”

Section: ) Proposed Charge Pump Circuitmentioning

confidence: 99%

A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

Schober

Choma

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a wide-operating range analog phase locked loop (PLL) constructed from all-digital integrated circuit (IC) process components. Specifically, this work introduces 2 cutting-edge, scalable analog circuit designs for a charge pump (CP) and a voltage controlled oscillator (VCO). The ultra-low power and highly accurate CP circuit uses 6 minimum-sized transistors, a small metal interconnect capacitor, and, unlike the state-of-the-art, no current mirrors. The ring VCO has a reconfigurable, expandable structure and is capacitively tunable allowing for an exceptionally large frequency operating range of 0.8 to 28.2GHz making it suitable for variety of wireless and wireline applications. The PLL has been fabricated in a TSMC 40nm all-digital CMOS process and physically tested with a 0.5-1.2V supply. The fabricated PLL has an area of 0.0048mm 2 , consumes a maximum of 1.25mW, and has a 0.82 ±0.0275ps RMS jitter over the entire operating range.

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Section: ) Proposed Charge Pump Circuitmentioning

confidence: 99%

A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

Schober

Choma

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…An all-digital PLL (ADPLL) has been widely explored to overcome these challenges [1]- [3]. However, because of the quantization noise from a time-to-digital converter (TDC) and a digitally controlled oscillator, and the power consumption by the TDC and a digital loop filter, there are still a lot of demands for analog PLLs in low-power and high-performance applications [4]- [8]. One of the most critical challenges of the CP-PLL in deep-submicron CMOS technology is a reference spur due to a leakage current of a loop filter capacitor [9].…”

Section: Introductionmentioning

confidence: 99%

Reference Spur Reduction Techniques for a Phase-Locked Loop

Bae

Jeong

et al. 2019

IEEE Access

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This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead. This leakage compensation loop senses the leakage current of the loop filter from the up and down pulse widths in the steady state and compensates for the charge loss due to the leakage current. A systematic approach for the reference spur reduction is also proposed. Since a PLL operates as a band pass filter in the frequency domain, the reference spur can be filtered out by cascading the PLLs. The optimization technique for the cascaded PLLs is presented that minimizes the reference spur without degrading the phase noise performance. The proposed techniques are verified using an 800-MHz PLL chip fabricated in 65-nm CMOS process. The prototype PLL achieves the reference spur of −68.57 dBc while the conventional charge-pump PLL without the proposed spur reduction techniques achieves −42.83 dBc. INDEX TERMSCascaded phase-locked loop, charge pump, leakage current, phase-locked loop, reference spur.

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A Novel Low Voltage Hybrid Phase Locked Loop

Ram

Hegde

2017

2017 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

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A charge transfer-based high performance, ultra-low power PLL charge pump

Cited by 4 publications

References 5 publications

A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

Reference Spur Reduction Techniques for a Phase-Locked Loop

A Novel Low Voltage Hybrid Phase Locked Loop

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A charge transfer-based high performance, ultra-low power PLL charge pump

Cited by 4 publications

References 5 publications

A 1.25mW 0.8&#x2013;28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

A 1.25mW 0.8&#x2013;28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

Reference Spur Reduction Techniques for a Phase-Locked Loop

A Novel Low Voltage Hybrid Phase Locked Loop

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Product

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A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

A 1.25mW 0.8–28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS