A Chip-Level Optical Interconnect for CPU

Hao, Qinfen; Qin, Mengyuan; Qi, Nan; Xue, Haizhou; Han, Meng; Li, Xin; Hao, Kai; Niu, Xiaodi; Xiao, Limin; Fan, Dongrui; Kurata, K.

doi:10.1109/lpt.2021.3084945

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…Intel [141] integrates the SerDes, TIA/Driver, and optic parts into a photonic IC, while HP [242] integrates the payload IC, SerDes, and TIA/Driver into a single chip. ICT [243] chooses to integrate the payload IC, SerDes, and optical parts in a single chip by co-package technology, but with a standard interface between these parts.…”

Section: Technology and Market Challengesmentioning

confidence: 99%

Co-packaged optics (CPO): status, challenges, and solutions

Tan

Liu³

et al. 2023

Front. Optoelectron.

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Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology. Graphical Abstract

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Section: Technology and Market Challengesmentioning

confidence: 99%

Co-packaged optics (CPO): status, challenges, and solutions

Tan

Liu³

et al. 2023

Front. Optoelectron.

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“…For more information, see https://creativecommons.org/licenses/by/4.0/ ASIC reducing the length of electrical channels [17], [18]. This has opened the doors for co-packaged optics (CPO) or first-level package integration [11], [15], [16], [19], [20], [21], [22], [23], [24], [25] as well as integration of silicon photonics (SiP) along with CMOS switch ASIC [26], [27], [28], [29], [30], [31], [32], [33], [34].…”

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confidence: 99%

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

Patel

Sharif-Bakhtiar

Carusone

2023

IEEE J. Solid-State Circuits

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A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with −8.2-dBm sensitivity is presented in support for optical receivers required in the next-generation intradata center links. A proposed three-stage TIA is comprised of a shunt-feedback stage followed by digitally programmable continuous-time linear equalizers (CTLEs) and a variable gain amplifier (VGA). Broadband low-noise design is achieved by having the first stage with much lower bandwidth (BW) followed by the proposed BW recovering CTLEs. A low-power design is supported by the inverter-based single-ended architecture with a single-ended-to-pseudo-differential conversion in the last stage. TIA's BW extension is further supported by optimizing the photodiode-to-receiver (PD-to-RX) interconnect and utilizing several inductive peaking techniques. It achieves 63-dB gain, 32-GHz BW, and an average input-referred current noise density of 16.9 pA/ √ Hz while operating at 0.9-V supply and consuming 47-mW power. Opto-electrical measurements are performed on a co-packaged prototype comprised of identical proposed TIAs in CMOS with combinations of various commercial PDs and PD-to-RX interconnect lengths confirming 112-Gb/s 4-PAM reception meeting pre-forward error correction (FEC) symbol error rate (SER) of 4.8 × 10 −4 without any post-equalization. Index Terms-100 Gb/s, 400 GbE, CMOS, co-packaged optical receiver front end, continuous-time linear equalizer (CTLE), fin field effect transistor (FinFET), gigabit Ethernet, inverter, low-noise broadband amplifier, optical communications, PAM-4, transimpedance amplifier (TIA). I. INTRODUCTIONT HE Big Bang of the Internet powering 5G, artificial intelligence (AI), machine learning (ML), video conferencing, the Internet of Things (IoT), and cloud storage applications has continuously increased the demand on the

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