A circuit approach to LTL model checking

Abstract

This paper presents a method for translating formulas written in assertion languages such as LTL into a monitor circuit suitable for model checking. Unlike the conventional approach, no automata is generated for the property, but instead the monitor is built directly from the property formula through a recursive traversal. This method was first introduced by Pnueli et. al. under the name of Temporal Testers. In this paper, we show the practicality of temporal testers through experimental evaluation, as well as offer a self-contained exposition for how to construct them in manner that meets the requirements of industrial model checking tools. These tools tend to operate on logic circuits with sequential elements, rather than transition relations, which means we only need to consider so called positive testers with no future references. This restriction both simplifies the presentation and allows for more efficient monitors to be generated. In the final part of the paper, we suggest several possible optimizations that can improve the quality of the monitors, and conclude with experimental data.

Verification and Synthesis of Clock-Gated Circuits

“…The second set of experiments compares the scalability of the three above methods by applying them to the same design (qmult taken from OpenCores [33]), but with varying bit-widths (8)(9)(10)(11)(12)(13)(14)(15)(16). As the widths increase, the combinational part gets more complex.…”

“…Claessen et al [10] provided methods for expressing LTL/PLTL formulae as circuits. including G(z ⇒ {op}(a) and G(z ⇒ [a{op}b]), where {op} is an arbitrary LTL or PLTL operator.…”

“…Representing an observable condition is challenging because it relates to future circuit behaviors; thus extra FFs are added to be used to verify future properties. In the following, we just describe the hardware constructions for the future properties, but refer to [10] for the more complicated constructions and their justifications. Free variables z X and z U are added to transform an LTL formula into an equi-satisfiable one.…”

“…To build O in , the observable condition O out , for the gated FF output, can be used with extra signals (z i , pending i , f ailed i and accept i ), en old and en new as shown in Figure 5 After constructing all signals required by Formula 5.1, the algorithm proposed in [10] is used to verify the observability clock-gating condition. For further details, please refer to the reference cited.…”

MightyL: A Compositional Translation from MITL to Timed Automata

“…Alternatively, [8] gives a symbolic encoding of alternating automata which can be used directly with NuSMV [13], but minimality of transitions (which may potentially improve the performance of verification algorithms, cf. [21]) is difficult to enforce in this setting (see also [14,34]). Our construction combines the advantages of these approaches-it can be regarded as a symbolic encoding of OCATAs in TAs, enforcing some minimality criteria on transitions for efficiency (see Section 6)-and provides compatibility with existing tools that construct state spaces on-the-fly.…”