A circuit design for the improvement of radiation hardness in CMOS digital circuits

Chen, C.-C.; Liu, S.-C.; Hsiao, C. C.; Hwu, Jenn–Gwo

doi:10.1109/23.277496

Cited by 15 publications

(2 citation statements)

References 8 publications

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“…Integrated circuits are widely employed in these applications to achieve improvements in the performance and, at the same time, reduce the weight, volume and power consumption. This is especially critical in space instrumentation, due to the current trends of costs reduction may affect to the operating frequency and also to the correct functionality of the analogue section [12].…”

Section: Introductionmentioning

confidence: 99%

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

Sordo-Ibáñez

Piñero-García

Muñoz-Díaz

et al. 2016

IEEE Trans. Nucl. Sci.

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This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35 µm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between-25 and 125 ºC) and a total dose beyond 300 krad. Index Terms-nuclear instrumentation and measurement; space applications; CMOS mixed-signal ASICs; front-end electronics; RHBD; dual-slope ADC.

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Section: Introductionmentioning

confidence: 99%

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

Sordo-Ibáñez

Piñero-García

Muñoz-Díaz

et al. 2016

IEEE Trans. Nucl. Sci.

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“…An improvement in radiation hardness can arise either by better controlling process parameters during device fabrication or by improvement in layout and design of the circuit [l], [2]. Work has been done in improving radiation hardness of Si and GaAs SRAMs, [3], [4] against SEUs.…”

Section: Introductionmentioning

confidence: 99%

Total dose radiation hardening and testing issues of GaAs static memories

Srivastava

Ganeshan²

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test

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A test chip in G a A s (E/D) technology has been designed and implemented in 1.2 p m MOSIS G a A s design rules. T h e unpackaged devices have been subjected to 1.5 keV A1 -K , X-rays and degradations in zero bias threshold voltage and device transconductance of n-channel E and D-MESFETs have been studied. A modified G a A s S R A M cell design, incorporating a circuit design t o minimize degradations in noise margindue t o degradations in device parameters at large radiation doses has been proposed.

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Radiation Effects and Circuit Hardening

2002

Cmos Memory Circuits

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The advent of extraterrestrial space utilization, and the requirements to operate many advanced military and some commercial systems in radioactive environments, brought the radiation hardening of semiconductor integrated circuits to the mainstream of the technological developments. Among the various CMOS integrated circuit types, the CMOS memory circuits manifest the highest susceptibility to the effects of radioactive radiation events and, usually, their hardness limits the applicability of the system in radiation environments. To improve the radiation hardness of CMOS memories special processing, device and circuit techniques can be used. This final chapter introduces those radiation effects on CMOS-bulk and CMOS SOI (SOS) transistor devices and circuits which are important to memory designs, and discloses the circuit and design techniques which may be applied to enhance the radiation hardness of CMOS-bulk and CMOS SOI (SOS) memories. The presentation of CMOS SOI (SOS) supports both hardened and nonhardened designs and includes the effects of floating substrates, side-and back-channels, and diode-like nonlinear elements. Radiation Effects Radiation Hardening Designing Memories in CMOS SOI (SOS)

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A circuit design for the improvement of radiation hardness in CMOS digital circuits

Cited by 15 publications

References 8 publications

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

Total dose radiation hardening and testing issues of GaAs static memories

Radiation Effects and Circuit Hardening

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