A class-G dual-supply switched-capacitor power amplifier in 65nm CMOS

Yoo, Sang-Min; Jann, Benjamin; Degani, Ofir; Rudell, Jacques C.; Sadhwani, R.; Walling, Jeffrey S.; Allstot, D.J.

doi:10.1109/rfic.2012.6242271

Cited by 10 publications

(3 citation statements)

References 6 publications

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“…The efficiency improvement comes from the fact that for lower signal levels, the low power part operates twice as efficiently as its high power counterpart. Therefore, this is beneficial when signals are applied that typically don't often need the high output power [23]. …”

Section: Class Gmentioning

confidence: 99%

Efficiency Enhancement Techniques for RF and MM-Wave Power Amplifiers

Reynaert

Francois

2016

Efficient Sensor Interfaces, Advanced Amplifiers and Low Power RF Systems

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Some important aspects of CMOS RF PA design are discussed. First the reader is confronted with the ever prominent efficiency-linearity trade-off in the design of conventional amplifier classes, such as A and B, as well as the challenge to achieve high output power in low-voltage CMOS. To cope with this challenge, several power combining structures are introduced. Next, some RF PA architectures are presented to improve the efficiency at power back-off. Finally, some recently introduced architectures are discussed that use the advanced signal processing capabilities of CMOS to deal with this efficiency-linearity trade-off in RF PA design.

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Section: Class Gmentioning

confidence: 99%

Efficiency Enhancement Techniques for RF and MM-Wave Power Amplifiers

Reynaert

Francois

2016

Efficient Sensor Interfaces, Advanced Amplifiers and Low Power RF Systems

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“…One specific architecture of RF-DACs is the so-called capacitive RF-DAC or switched-capacitor PA (SCPA), which was first published in the literature by Yoo et al [18]- [20]. The capacitive RF-DAC combines high linearity over a wide frequency range with high power efficiency [18].…”

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confidence: 99%

A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

Trampitsch

Kalcher²,

Enzinger³

et al. 2021

IEEE Trans. Microwave Theory Techn.

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This article presents a novel digital predistortion (DPD) approach to compensate for nonlinear dynamic distortions caused by the supply network of capacitive radio frequency digital-to-analog converters (RF-DACs). The developed DPD concept recreates the voltage distortion on the RF-DAC's supply network and modulates the input signal such that the effects on the output signal of the RF-DAC are canceled. In contrast to conventional DPD approaches such as pruned Volterra series or memory polynomials, the complexity of the proposed concept is reduced to a feasible level, allowing for implementation in integrated circuits. Furthermore, the derived DPD model allows to use linear estimation algorithms for coefficient training. The presented DPD is demonstrated by measurements of two different capacitive RF-DAC designs and compared with conventional DPD approaches. EVM and adjacent channel power ratio (ACPR) can be improved by up to 6 and 7 dB, respectively, outperforming conventional approaches. Index Terms-Digital predistortion (DPD), memory effects, memory polynomial (MP), power amplifier (PA), radio frequency digital-to-analog converter (RF-DAC), switched-capacitor power amplifier (SCPA), Volterra series. I. INTRODUCTION T HE demand for high data rates, robust transmissions, and power efficiency poses stringent requirements on the design of integrated wireless transceiver systems. Increasing the data rate, while simultaneously providing a reliable and power-efficient transmission, is closely related to the linearity of the communication systems. In radio frequency (RF) wireless communication transmitters, the key component in terms of linearity and Manuscript

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“…Hence, digital predistortion could be needed [72]. Yoo et al [73,74] proposed a digitally-controlled switchedcapacitor RF PA (SCPA) with Class G architecture to further increase linearity and efficiency as shown in Figure 3.12. However, their output matching network, which could be a source of power losses, parasitics and complexity of design, was done off-chip to reduce the die area.…”

Section: Envelope Tracking Pa Topologymentioning

confidence: 99%

An approach for circuit design optimization based on complexity considerations

Tan¹

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Optimizing circuit trade-offs is a highly challenging task for any design team. This challenge is further exacerbated with the additional design complexity of integrating multiple circuits. Today, with the increasing demand for newer wireless communication products, design teams face a shorter time-to-market (TTM) for every generation of their new products and each product requires major improvement in wireless capability. Hence, it is important for the design teams to design circuits with complexity in mind. A design approach divided into architecture complexity, component complexity and discretional complexity are proposed. A novel benchmarking figure-of-merit, complexity factor (CF), was formulated and proposed for the architecture complexity. A simulated application of a goal, gain optimization, demonstrated and revealed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for ultra-high frequency (UHF) applications. As the number of variables to be permuted is very high for the power amplifier (PA) blocks from circuit down to the process level, it is treated as a black box in the analysis but the next topology complexity step addressed this. A topology comparison was proposed between a 2-stacked EDNFET and SGNFET and a 4-stacked resistorladder SGNFET PA. Both of them achieved a near 20dBm output power and approximately 60% efficiency on the test-chips measurements, which demonstrated that the 2-stacked EDNFET and SGNFET topology with a reduction in stack height is a potential candidate for a reduced difficulty and complexity Doherty power amplifier (DPA) design. In the discretional complexity step, we explored the linearization of the DPA and proposed a DPA with a gm3 cancellation bias scheme tapping on its intrinsic linearization property, without adding external circuity to XII increase the complexity of the overall circuit but at the same time, improve its linearity by 6-8dB compared to a DPA optimized for power and more than 9dB compared with a balance PA with a similar structure. XIII

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A class-G dual-supply switched-capacitor power amplifier in 65nm CMOS

Cited by 10 publications

References 6 publications

Efficiency Enhancement Techniques for RF and MM-Wave Power Amplifiers

Efficiency Enhancement Techniques for RF and MM-Wave Power Amplifiers

A Circuit-Inspired Digital Predistortion of Supply Network Effects for Capacitive RF-DACs

An approach for circuit design optimization based on complexity considerations

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