A class of power efficient VLSI architectures for high speed turbo-decoding

Bougard, Bruno; Giulietti, Alexandre; Perre, Liesbet Van der; Catthoor, Francky

doi:10.1109/glocom.2002.1188139

Cited by 19 publications

(15 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…T hese soluti on s combined w ith a sys tem ati c data transfe r and storage exploration mad e possible designing a high throu ghput. low power arch itec ture mapped into a turb o cod ec ASIC The resulting architecture based on parallel windows can be easily tun ed to different app lications [31]. Th e presented tur bo codec proves that it is po ssible tl ha ve turb o coding with low latency.…”

Section: Discussionmentioning

confidence: 99%

“…Although some of the parameters (e.g. block size) were defined based on the Hiperlan2 standard, the final architecture showed to be very flexible and easily reconfigurable [31]. Starting with a thorough algorithm exploration that defined the best turbo coding scheme combined with the best set of parameters, we carried on with architecture exploration and optimization based on a systematic data transfer and storage exploration [l0].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Turbo Coding for 4G Systems: Design Issues and Solutions

Giulietti¹,

Strum²,

Bougard³

et al. 2003

Journal of Communication and Information Systems

Self Cite

View full text Add to dashboard Cite

-After the initial interest caused by the appearance of turbo codes in 1993. special attention on the implementation has Jed to their adoption in some of the most important 3G standards. However. future broadband systems (with data rates up to 155 Mbis) still require a better speed/latency/power performance than those found in current implementations. This paper discusses several design aspects of a broadband. low-power turbo codec owning features that enable its application in the incoming decade systems. The presented ideas were applied to an 80 Mb/s, 2 nJ/bit turbo codec core with latency smaller than 10ms. This flexible architecture allows re-scaling towards faster low power implementations (beyond I Gb/s).Keywords: Turbo codes. VLSI. low-power. broadband. Resumo -Ap6s 0 interesse inicial causado pelo surgimento dos c6digos turbo em 1993. uma atencao especial para a implernentacao levou a sua utilizacao em alguns dos mais importantes padroes 3G. Entretanto. os futuros sistemas de faixa larga (com taxas de dados de ate 155Mb/s) requerem um desempenho de velocidade/latencia/potencia ainda melhor do que aquele encontrado nas atuais implementacoes. Esse artigo discute diversos aspectos de projeto de um codec turbo de baixa potencia cujas caracteristicas possibilitam a sua aplicacao nos sistemas da proxima decada, As ideias apresentadas foram aplicadas a urn codec turbo operando a 80 Mb/s e 2nJ/bit com latencia menor do que lOms. Essa arquitetura Hexi vel permite reescalonamento. na direcao de se ter implernentacoes de mais baixa poiencia e mais rapidas (acima de I Gb/s).Palavras-chave: C6digos turbo, VLSL baixa potencia, faixa larga.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Turbo Coding for 4G Systems: Design Issues and Solutions

Giulietti¹,

Strum²,

Bougard³

et al. 2003

Journal of Communication and Information Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…After the addition between the path metrics ( 0 [ ] P n to 3 [ ] P n ) and the branch metrics ( 0 γ to 3 γ ), the four addition results which are called pre-compare metrics ( A P to D P ) should be compared for finding the maximum value. As indicated in Fig.…”

Section: Retiming Of Lut-based Radix-4 Acs Unitmentioning

confidence: 99%

“…To increase the throughput of SISO decoders, there are several methods such as the increase of parallelism of decoder [1][2][3][4][5][6][7][8][9][10], the improvement of operating frequency [11], and the high radix architecture [12][13][14]. This paper is focused on high operating frequency of radix-4 ACS unit for the high-throughput of radix-4 SISO decoders.…”

Section: Introductionmentioning

confidence: 99%

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

Byun

Kim

Kim³

2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

show abstract

“…Turbo decoder VLSI architectures have also been extensively investigated by many researchers [5,8,20,21,25,30,33,41,44]. However, designing a flexible decoder to support both LDPC and Turbo codes still remains very challenging.…”

Section: Introductionmentioning

confidence: 99%

A Flexible LDPC/Turbo Decoder Architecture

Sun

Cavallaro

2010

J Sign Process Syst

View full text Add to dashboard Cite

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm 2 . The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE

show abstract

A class of power efficient VLSI architectures for high speed turbo-decoding

Cited by 19 publications

References 13 publications

Turbo Coding for 4G Systems: Design Issues and Solutions

Turbo Coding for 4G Systems: Design Issues and Solutions

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

A Flexible LDPC/Turbo Decoder Architecture

Contact Info

Product

Resources

About