A clock distribution network for microprocessors

Abstract

A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of buffered. tunable tree networks. with the final trees all driling a common grid. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune a single interconnect network with 6 meters of wire and 50.000 resistors.capacitors. and inductors. Global clock skew as low as 22 ps was measured for large microprocessor chips.

Power and performance evaluation of globally asynchronous locally synchronous processors

“…Restle et al [11] and Bailey and Benschneider [12] give a good overview of clocking system design for high-performance processors.…”

Power efficiency of voltage scaling in multiple clock, multiple voltage cores

“…Restle et al have argued in [17] that clock skew arises mainly due to process variations in the tree of buffers driving the clock. Since device geometries will continue to shrink and clock frequencies and die sizes will continue to increase, global clock skew induced by such process variations can only get worse.…”

Grid-to-ports clock routing for high performance microprocessor designs

“…In today's high performance systems, clock signals are distributed through a global clock grid [6][7][8][9][10], followed by postgrid routing that connects clock loads to the grid. Early studies showed that most of the clock power dissipation was due to three major categories of capacitances -clock load, clock twig and clock mesh wires, and clock grid buffers.…”