A clock-gating method for low-power LSI design

Kitahara, Takeshi; Minami, Fumihiro; Ueda, T.; Usami, Kimiyoshi; Nishio, S.; Murakata, M.; Mitsuhashi, T.

doi:10.1109/aspdac.1998.669476

Cited by 18 publications

(10 citation statements)

References 14 publications

(11 reference statements)

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“…Brooks and Martonosi proposed a hardware mechanism for general-purpose microprocessors that dynamically changes the wordlength from a full 64-bit width to a narrower bit width depending on the application [4]. Clock gating has been used for reducing power by disabling value changes in unneeded functional circuits [11]- [13]. Other similar approaches have been presented [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation

Yoshizawa

Miyanaga

2008

IEEE Trans. Circuits Syst. I

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Wordlength determination is an indispensable task in digital hardware implementations of signal processing algorithms because the wordlength affects power consumption and system performance. There is a tradeoff between power consumption and system performance when searching for the optimum wordlength. We have developed a technique of dynamically controlling the wordlength used in the signal processing algorithms of wireless orthogonal frequency-division multiplexing (OFDM) receivers. The receiver dynamically changes the wordlength on the basis of the conditions in the propagation environment while satisfying the user-required communication quality. That is, the system optimizes the wordlength while operating by sensing its own performance and gradually adjusting this wordlength to improve performance. Testing revealed that, for a packet error rate (PER) of 10 2 , the application of this technique to an OFDM receiver reduces energy dissipation by 18.1%-30.2%.

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Section: Introductionmentioning

confidence: 99%

Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation

Yoshizawa

Miyanaga

2008

IEEE Trans. Circuits Syst. I

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“…Twenty percent to fifty percent of the power usage is contributed by the clock network [10]. On behalf of power reduction, the application of clock gating is an effective approach in the sequential circuits.…”

Section: Introductionmentioning

confidence: 99%

Clock Network Synthesis with Concurrent Gate Insertion

Chow

Sham

2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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Abstract. In VLSI digital circuits, clock network plays an important role on the total performance of the chip. Clock skew and power dissipation are two major focuses of concerns in the clock network synthesis. During topology generation, the locations of buffer and gate insertion are usually not available. Despite local optimization, the global performance is limited. In this paper, a novel approach of topology generation with concurrent gate insertion is proposed. Meanwhile, a strict clock slew constraint is applied with comprehensive buffer insertion techniques. By clock gating, the switched capacitance of the clock tree is reduced, with acceptable extra cost caused in controller tree. In experimental results it is shown that our approach has good performance on the reduction of both clock skew and power dissipation.

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“…Therefore, we only consider dynamic power minimization in this paper. The definition of the dynamic power is shown as follows: (2) where means the total load capacitance on the circuit, is the frequency of the clock signal and is the power supply. means the amount of switching times of the corresponding signal in each clock cycle.…”

Section: Switched Capacitancementioning

confidence: 99%

“…Additionally, the clock signal is also the single largest source of dynamic power usage in the system. There is around 30% to 50% of the chip power which is consumed by the clock tree [2]. Owing to the high frequency of switching as well as the expansion of the clock tree over the whole chip, a huge amount of energy dissipation is consumed by the clock tree.…”

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confidence: 99%

Fast Power- and Slew-Aware Gated Clock Tree Synthesis

Chow

Sham

2012

IEEE Trans. VLSI Syst.

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Abstract-Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power-and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.

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A clock-gating method for low-power LSI design

Cited by 18 publications

References 14 publications

Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation

Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation

Clock Network Synthesis with Concurrent Gate Insertion

Fast Power- and Slew-Aware Gated Clock Tree Synthesis

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