A closed-form capacitance model for tunnel FETs with explicit surface potential solutions

Abstract

General analytical Poisson solution for undoped generic two-gated metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 90, 012110 (2007);In this paper, a closed-form physical capacitance model for bulk tunnel FETs (TFETs) is proposed based on the surface potential approach for the first time. Fundamentally different from that in the MOSFET, the channel surface potential u sf in the TFET is alternately controlled by the drain bias and gate bias in different operation regions. On the basis of physical insight into the operation mechanism, the analytical model of u sf as a function of terminal bias is established. The Gaussian box is introduced to predict the surface potential profile near the source-body junction. Furthermore, the surface-potential-based capacitance model is derived and the calculated terminal capacitances show good agreement with the TCAD simulation results. With the essential physics considered, excellent validity of the model is achieved for bulk TFETs with a large range of structure parameters and SOI/double-gate (DG) TFETs. V C 2014 AIP Publishing LLC.

Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

“…The gate-drain capacitance is calculated by adding C gd,inv and C gd,inf . Inversion layer charges are contributed by drain voltage [22]. As in the depletion region, there is no inversion charge present.…”

“…The second component of gate-drain capacitance depends on the inner fringing field of the gate. The gate-drain inner fringing field can be defined as [22,32] C gd, inf =…”

“…2 shows the relationship between the total gate capacitance (C gg ), gate-source capacitance (C gs ) and gate-drain capacitance (C gd ). Here, it is clearly observable that the total gate capacitance is dominantly shared by the gatesource capacitance and less is shared by the gate-drain capacitance unlike TFETs having full gate channel [20][21][22]. Owing to large gate-source overlap in GOSC TFET, the depletion and the overlap capacitance are increased and due to large gate-drain underlap the amount of inner fringing field is reduced.…”

“…There is an enormous advancement in the field of TFET geometrics and DC characteristics modelling compared with that less amount of work has been done in the field of analysis and modelling of different TFET capacitances. Few models have been reported till date [20][21][22]. A capacitance model has been derived to analyse the capacitance components of TFET by Yang et al [20] and comparison has been studied in between conventional SOI TFET and conventional SOI MOSFET.…”

“…Therefore, this model cannot be applied to other structures. The capacitance model is derived by Wang et al [22] for different conventional TFETs. The capacitance is deeply dependent on the geometry of the device.…”