A Closer Look at Intel Resource Director Technology (RDT)

Sohal, Parul; Bechtel, Michael; Mancuso, Renato; Yun, Heechul; Krieger, Orran

doi:10.1145/3534879.3534882

Cited by 14 publications

(3 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Architecture-level features such as Arm's MPAM (ARM 2022a) or Intel's RDT (Intel 2024) aim to deliver improved (QoS) control over the memory subsystem. Real-time characteristics of RDT are analyzed by Sohal et al (2022) and a theoretical analysis of MPAM characteristics is presented by Zini et al (2023). Unfortunately, the availability of such architectural-level features on current systems is still very limited.…”

Section: Related Workmentioning

confidence: 99%

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Zuepke,

Bastoni,

Chen

et al. 2024

Real-Time Syst

Self Cite

View full text Add to dashboard Cite

In today’s multiprocessor systems-on-a-chip, the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time analysis. Memory regulation via throttling is one of the most practical techniques to mitigate interference. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and conduct an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.

show abstract

Section: Related Workmentioning

confidence: 99%

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Zuepke,

Bastoni,

Chen

et al. 2024

Real-Time Syst

Self Cite

View full text Add to dashboard Cite

show abstract

“…Additionally, in multicore virtualization, resources that are shared among the VMs, such as the caches and I/O interfaces (e.g., busses), can cause performance degradations of co-located VMs due to mutual interference [203]. Hence, hardware assistance for virtualized entities, e.g., using ISA extensions, such as the Cache Allocation Technology (CAT) and Memory Bandwidth Allocation Technology (MBA) [204], [205] that are part of the Intel® Resource Director Technology (RDT) [206], can streamline the deployment process to provide the performance isolation of VMs. However, some platforms do not feature hardware-assisted virtualization and therefore cannot employ these hardware-assistance technologies.…”

Section: B: Hypervisor Performancementioning

confidence: 99%

“…We focus on Proteus [156], which is a real-time bare-metal hypervisor that targets multi-core platforms. Proteous supports both para-virtualization and full virtualization (without the use of hardware assistance, i.e., without ISA improvements, e.g., without Intel® Resource Director Technology (RDT) [206]) to achieve performance isolation between the VMs with strict performance characteristics as is required for real-time NF applications. Proteus ensures spatial and temporal separation of guest VMs.…”

Section: B: Hypervisor Performancementioning

confidence: 99%

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

et al. 2022

View full text Add to dashboard Cite

Scalable and flexible communication networks increasingly conduct the packet processing for Network Functions (NFs) in General Purpose Computing (GPC) platforms. The input/output (I/O)-intensive and latency-sensitive packet processing is challenging for the operating systems and hypervisors running on GPC platforms. This article surveys the existing enabling technologies and research studies on operating system and hypervisor aspects that directly influence the packet processing for NFs on GPC platforms. We organize this survey according to the main categories abstraction approach, memory access, and I/O strategy. We further categorize abstraction approach technologies and research studies into the categories operation systems, hypervisors, and containers. We partition the memory access category into the two subcategories of memory allocation and memory access, while we partition the I/O strategy category into the sub-categories I/O device virtualization and I/O device access. Our survey gives a comprehensive summary of the capabilities and limitations of the existing enabling technologies and researched approaches for abstraction, memory access, and I/O for NF packet processing. We outline critical future research directions for advancing NF packet processing on GPC platforms.

show abstract

Precise control of page cache for containers

Wang,

Wu,

et al. 2023

Front. Comput. Sci.

View full text Add to dashboard Cite

A Closer Look at Intel Resource Director Technology (RDT)

Cited by 14 publications

References 25 publications

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

Precise control of page cache for containers

Contact Info

Product

Resources

About