A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

Abstract

<p> In the realm of 3D monolithic integrated circuits, inter-layer vias are prone to defects during fabrication, assembly, and operation that necessitate robust Built-In Self-Test solutions. This paper introduces an innovative BIST design aimed at the detection and localization of different types of faults in irregularly placed ILVs using a walking pattern methodology. In the proposed BIST methodology, the ILVs are clustered based on the fault occurrence probability distribution. Then, an effective detection approach is developed for all stuck-at faults, bridging faults, and almost all multiple faults in a single cluster. This approach allows designers to adjust different parameters such as fault coverage percentage, fault localization, and test time in alignment with specific requisites. The proposed BIST method reduces test configurations to two and test time to just 20 cycles by dividing ILVs into more clusters, overcoming a key limitation of recent approach. This methodology also demonstrates improved efficiency in terms of power consumption, area, and hardware utilization, particularly for large-scale benchmarks. For instance, when considering LU32PEENG and the scenario where ILVs are divided into 64 clusters, the power, area, and hardware overhead are 0.82% and 1.03%, and 1.14%, respectively. </p>