2020
DOI: 10.1109/jssc.2019.2953832
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A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation

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Cited by 25 publications
(15 citation statements)
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“…The measurement setup is shown in Fig. 25 All the on-chip power consumptions (e.g. the PA array, encoders, deserializers, frequency divider, and sign map) are included for the system efficiency calculation.…”
Section: Measurement Resultsmentioning
confidence: 99%
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“…The measurement setup is shown in Fig. 25 All the on-chip power consumptions (e.g. the PA array, encoders, deserializers, frequency divider, and sign map) are included for the system efficiency calculation.…”
Section: Measurement Resultsmentioning
confidence: 99%
“…The Doherty PA exhibits efficiency enhancement at PBO and high average efficiency, which is demanded in modern wireless transmitter systems. To further improve the PBO efficiency, the multi-ways Doherty [22]- [25] and Class-G Doherty PAs [29], [30] are introduced with multiple efficiency peaks at PBO. Fig.…”
Section: A Review Of Multi-way Doherty and Class-g Doherty Pamentioning
confidence: 99%
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“…These modulation schemes feature a high peak-to-average-power ratio (PAPR) (e.g., >10 dB), which requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. Many efficiencyenhancement techniques, such as out-phasing [27]- [29], envelop-tracking (ET) [30], and Doherty [31]- [37], are currently adopted in various DPA topologies to enhance their efficiency at DPBO. Two-way Doherty DPAs (DDPAs) are popular due to their less complicated baseband processing and handling large modulation bandwidth, but they typically enhance efficiency at 6 dB PBO.…”
mentioning
confidence: 99%
“…However, it is incredibly challenging to implement an N-way DDPA since incorporating more DPA banks leads to excessive power combiner losses. In [31], a three-way DDPA architecture with decent overall linearity/efficiency performance has been reported.…”
mentioning
confidence: 99%