A CMOS 6-Bit 16-GS/s time-interleaved ADC with digital background calibration

Huang, Chun-Cheng; Wang, Chung-Yi; Wu, Jieh-Tsorng

doi:10.1109/vlsic.2010.5560312

Cited by 26 publications

(9 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Time-interleaved ADCs have previously been considered impractical because the solution for this issue is much more complicated than the PN injection for gain and offset errors. Recently, several solutions have been proposed [34][35][36], and the timeinterleaved architecture has become popular for high-speed A/D conversion. One of these solutions is based on digital correlation between the two interleaved channels [36].…”

Section: ) Detection Of Sampling Instant Mismatch By Correlationmentioning

confidence: 99%

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

Shu

Ho²,

Chen

et al. 2016

SIP

View full text Add to dashboard Cite

show abstract

Section: ) Detection Of Sampling Instant Mismatch By Correlationmentioning

confidence: 99%

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

Shu

Ho²,

Chen

et al. 2016

SIP

View full text Add to dashboard Cite

show abstract

“…In this thesis we consider only linear mismatch errors which typically dominate [15]. More specifically, since gain and offset errors can be easily compensated, here we deal with only time-skew mismatch errors which occur as a result of nonuniform time skews between the sampling clocks of the channel ADCs [16][17][18]. In practice, the time-skew errors can be assumed to be frequency independent only up to a certain output resolution and bandwidth [19].…”

Section: Chapter 1 Backgroundmentioning

confidence: 99%

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Pillai¹

2015

View full text Add to dashboard Cite

An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TI-ADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs.iii Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor.Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lowe...

show abstract

“…However it is really sensitive to analog filter errors and imperfections, necessitating high resource calibration technique. The most natural solution employs time-interleaving [35] giving outstanding performance in terms of speed. But it lacks the resolution and dynamic range.…”

Section: Adc and Dac Challengesmentioning

confidence: 99%

Cognitive Radio RF: Overview and Challenges

Nguyen

Villain²,

Guillou³

2012

VLSI Design

View full text Add to dashboard Cite

Cognitive radio system (CRS) is a radio system which is aware of its operational and geographical environment, established policies, and its internal state. It is able to dynamically and autonomously adapt its operational parameters and protocols and to learn from its previous experience. Based on software-defined radio (SDR), CRS provides additional flexibility and offers improved efficiency to overall spectrum use. CRS is a disruptive technology targeting very high spectral efficiency. This paper presents an overview and challenges of CRS with focus on radio frequency (RF) section. We summarize the status of the related regulation and standardization activities which are very important for the success of any emerging technology. We point out some key research challenges, especially implementation challenges of cognitive radio (CR). A particular focus is on RF front-end, transceiver, and analog-to-digital and digital-to-analog interfaces which are still a key bottleneck in CRS development.

show abstract

A CMOS 6-Bit 16-GS/s time-interleaved ADC with digital background calibration

Cited by 26 publications

References 3 publications

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges

Signal Reconstruction Algorithms for Time-Interleaved ADCs

Cognitive Radio RF: Overview and Challenges

Contact Info

Product

Resources

About