Abstract:On-chip power grid design is a major challenge in submicron technologies. High peak current coupled with inductive reactance of supply mesh results in power integrity issue results in ringing. This supply noise reduces the available differential voltage for sensing and results in read failure in Read only memory (ROM). Controlling the noise by using large decoupling capacitor is area consuming. Proposed scheme uses a noise tolerant reference generation. Scheme reduces the coupling effect of noise on differenti… Show more
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