A CMOS Batcher and Banyan chip set for B-ISDN packet switching

Marcus, W.S.

doi:10.1109/4.62170

Cited by 20 publications

(8 citation statements)

References 4 publications

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“…Table III summarizes the chip characteristics. The length differences between the FIFOs allowed testing the do [2] do [3] do [1] do[0] ki di [2] di [3] di [1] di n-transistors, the internal nodes never fully switch to the rail voltage: improving speed and reducing power dissipation. For around twice the area (109µmx71µm), the asynchronous circuit ran about 10% faster than the equivalent synchronous circuit: 500 MHz in 2µ CMOS.…”

Section: Resultsmentioning

confidence: 99%

“…But now, when the clock is high, the master node is passed onto two slave nodes (ds and do) and the output (do). a P0 at the input (di=0111) this discharges do [1], causing the output to go into state P0 (0100). This in turn causes the acknowledge output to go into state P (ko=1).…”

Section: Dynamic Master-slave Latchmentioning

confidence: 99%

“…This latch guarantees refresh (see section V) every two inputs because the nodes ki and ko change every time data changes, and the nodes do [3] and do[0] are set every time ki is low and the nodes do [2] and do [1] are reset every time ki is high.…”

Section: B Asynchronous Master-slave Latchmentioning

confidence: 99%

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Dynamic asynchronous logic for high-speed CMOS systems

McAuley¹

1992

IEEE J. Solid-State Circuits

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As transistor switching speed improves, synchronizing a global clock increasingly degrades system performance. Therefore, self-timed asynchronous logic becomes potentially faster than synchronous logic. To do so, however, it must exploit the techniques used in fast synchronous designs, including: redundant logic, inverting logic, transistor size optimization, dynamic logic, and phase alignment. Most techniques can be applied equally well to asynchronous logic, indeed phase alignment is easier; but combining dynamic and asynchronous logic is more difficult. We must guarantee minimum refresh intervals, together with race and hazard free operation. This paper describes an initial chip implementation, that combines dynamic and asynchronous logic running at 500MHz in 2µm CMOS. With the addition of transistor size optimization, simulations show the same circuit running in the same technology at 800MHz. I. Introduction Some applications, especially those in telecommunications, need both the density of CMOS and high switching speed [1]. This paper describes an effort to build fast CMOS circuits without significantly losing the density benefit of CMOS, increasing the design complexity, or increasing production costs. Specifically, we propose that asynchronous logic, combined with other fast CMOS logic techniques, can help improve speed by removing the need to synchronize a global clock. Many of the fast CMOS design techniques in this paper are derived from the excellent work at Linkoping University [2] [3]. Recently, they produced a shift-register running at 450 MHz in 3µm CMOS [4]. The aim of this paper is to extend their ideas by removing even the single phase clock they use for synchronization. The resultant asynchronous designs produce speeds comparable with their results in current technologies (minimum transistor sizes over 1µm). We believe, however, that asynchronous logic is likely to become more attractive as CMOS technology allows faster transistors. Asynchronous communication is not new [5]. More recently, Martin has proposed a method of producing designs by compilation [6]; Sutherland proposed a method called micropipelines [7]; and we have described a method called 4-state coding [8]. These methods tend to emphasize the reliability or reduced design complexity of asynchronous designs. This paper concentrates on the potential of asynchronous designs for speed. We propose using acknowledged asynchronous logic for local on-chip communication and unacknowledged asynchronous phase alignment buffers for long distance chip-tochip communication. Although other asynchronous techniques can be used, we concentrate on a redundant variation of 4-state coding that is particularly well suited to fast implementation.

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Section: Resultsmentioning

confidence: 99%

Section: Dynamic Master-slave Latchmentioning

confidence: 99%

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Dynamic asynchronous logic for high-speed CMOS systems

McAuley¹

1992

IEEE J. Solid-State Circuits

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“…In simulation, the are set to match the queue state, and (1) is numerically integrated using a fifth-order adaptive step size algorithm [6]. [7], [8]. Circuits similar to (1) have been built with less than 1-s decision time [9].…”

Section: B Software (Sw) and Neural Network (Nn) Packet Arbitratorsmentioning

confidence: 99%

A high-performance two-stage packet switch architecture

Brown

1999

IEEE Trans. Commun.

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Abstract-This paper contributes a distributed packet controller which reduces queueing to a single stage in two-stage packet switches. Software and neural network based controllers are described. Simulations under a range of traffic conditions for a 1024 2 1024 switch size shows the simplest architecture has the best performance.Index Terms-Asynchronous transfer mode, neural networks, packet switching.

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“…The horizontal output H , has a packet if Hi or Di has a packet on it (either Pi or Ci is true) and this is indicated by Po being true. If there is a packet at the horizontal input Hj as indicated by Pi being true, then H, is connected to Implementation of the 2 x 4 switch element is similar to the implementation of the 2 x 2 Banyan element in [4]. Instead of two outputs of a Banyan element being selected from the two inputs, two out of the four outputs are selected from the two inputs in the 2 x 4 switch element.…”

Section: Implementation Considerationsmentioning

confidence: 99%

Design of a large ATM switch with trunk grouping

Aryal

Meditch

Proceedings of Fourth International Conference on Computer Communications and Networks - IC3N'95

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W e describe a large A T M switch with moderate circuit complexity which delivers packets in sequence with a small constant delay. The switch takes advantage of trunk grouping to increase throughput and has the same topology as that of a B a n an network. By using modules that look at k inputs 6 > 16) at a time and recursively dividing the packets into two groups, the proposed switch achieves a good throughput value that is relatively independent of switch size. Cell loss o n the oTder of can be obtained using the switch. The switch has O(nlog, n) complexity in the number of modules where n is the number of inputs. The modules of the switch have very regular interconnections, and hence are suitable f o r dense VLSI implementation.

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A CMOS Batcher and Banyan chip set for B-ISDN packet switching

Cited by 20 publications

References 4 publications

Dynamic asynchronous logic for high-speed CMOS systems

Dynamic asynchronous logic for high-speed CMOS systems

A high-performance two-stage packet switch architecture

Design of a large ATM switch with trunk grouping

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