A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

Boas, A. Vilas; Haddad, Sandro P.; Dias, José Antonio Siqueira

doi:10.1016/j.mejo.2014.01.010

Cited by 6 publications

(3 citation statements)

References 6 publications

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“…Their proposed LDO keeps the error amplifier gain higher than 50dB [22]. The operation of the LDO under dynamic load conditions was simulated using an SoC load model [42]. The power routing digital core of a microcontroller was back-annotated into a schematic view, resulting in an equivalent circuit with a total capacitance of 2.25 nF and 125,000 gates.…”

Section: Folded Compensation Cascode Topologymentioning

confidence: 99%

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

et al. 2022

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Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

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Section: Folded Compensation Cascode Topologymentioning

confidence: 99%

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

et al. 2022

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“…This ripple couples through

to the gate of the pass transistor and causes big overshoots/undershoots at the gate voltage. A large capacitor to the gate of the device is needed to attenuate them [ 13 ]. Increasing the capacitance of the gate of the pass transistor pushes the dominant pole to a lower frequency and decreases the unity gain bandwidth of the regulator.…”

Section: Ldo Linear Regulator Design Foundationsmentioning

confidence: 99%

An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications

Bahramali

López‐Vallejo

2021

Micromachines

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There are emerging applications, like bridge structural health monitoring, continuous patient condition and outdoor aiding of the elderly and the disabled, where Internet of things (IoT) nodes are used with very limited accessibility and no connection to the main supply network. They may also be exposed to harsh environmental conditions. These are applications where power and available area constraints are of great concern. In this paper, we design a 1.1 V low dropout (LDO) linear regulator in 40 nm technology to be embedded in IoT nodes. To address these constraints, we used state-of-the-art, variability-aware resistor-less sub-threshold biased CMOS-only ultra low power consumption configurations having low active area. The proposed LDO is internally compensated with embedded 18 pF Miller and 10 pF load capacitances. It can supply 1 mA maximum load current with 0.8 uA quiescent current. The dropout voltage of the regulator is 200 mV with minimum input voltage of 1.3 V. The efficiency of the regulator is 84%, which is about 99% of the maximum achievable efficiency for a 200 mV dropout voltage. The whole circuit, consisting of the embedded voltage reference and the Miller and load capacitances, takes less than 0.007 mm2 of the die size with 1 W power consumption.

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“…This ripple couples through C gs to the gate of the pass transistor and causes big overshoots/undershoots at the gate voltage. Therefore it needs to couple a large capacitor to the gate of the device in order to attenuate them [58]. Increasing the capacitance of the gate of the pass transistor pushes the dominant pole to a lower frequency and decreases the unity bandwidth of the regulator.…”

Section: Linear Regulator Conceptmentioning

confidence: 99%

Variability-aware design of front-end circuits for self-powered applications

Bahramali¹

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A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

Cited by 6 publications

References 6 publications

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

An RFID-Based Self-Biased 40 nm Low Power LDO Regulator for IoT Applications

Variability-aware design of front-end circuits for self-powered applications

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