A CMOS pulse-shrinking delay element for time interval measurement

Chen, P.; Liu, Shen-luan; Wu, Jingshown

doi:10.1109/82.868466

Cited by 154 publications

(62 citation statements)

References 8 publications

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“…As described, the pulse shrinking occurs because of the difference between the falling and the rising delays along the delay chain [2][3][4][5][6]. Without any bias adjustment, the pulse-shrinking mechanism with a dimension-controlled NOT gate was proposed to vary the size of the inhomogeneous (or pulse-shrinking) NOT gate to control the pulse-shrinking amount, as shown in Fig.…”

Section: Conventional Pulse-shrinking Mechanismmentioning

confidence: 99%

“…However, the calibration must be done continuously so as to consume much power. Without the bias voltage, a dimension-controlled version with a cyclic pulse-shrinking delay line was presented to greatly enhance the linearity and save the power [3]. The resolution is controlled by size ratio of adjacently inhomogeneous and homogeneous logic gates.…”

Section: Introductionmentioning

confidence: 99%

“…In additional to an absolute gate delay with an advanced CMOS technology, the approaches such as parallel scaled delay elements, Vernier delay lines, and time amplification can achieve a sub-gate delay resolution at the expense of circuit complexity and area. With low cost and simple circuit operation, the pulse-shrinking method has the possibility of reaching sub-gate resolution but without requiring circuit complexity [2][3][4][5][6]. When a pulse with a finite time width undergoes a pulse-shrinking unit to cause difference between the rising and the falling propagation times, the pulse width is shrinked by a small amount (i.e., time resolution).…”

Section: Introductionmentioning

confidence: 99%

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A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Chen¹,

Chen²,

You³

et al. 2017

dtetr

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Abstract.A new CMOS time measurement mechanism based on pulse shrinking applicable to time-to-digital converters (TDCs) is presented to improve resolution. In previous mechanism, the resolution was determined by controlling size ratio between an inhomogeneous and homogeneous logic gates to achieve sub-gate resolution. By only adding an inhomogeneous gate with identical size on the previous mechanism, the proposed mechanism possesses not only a resolution improvement but also a better resolution fluctuation for process and temperature variations. The proposed work was implemented in a 0.35-µm CMOS process for performance evaluation. The results demonstrated that the proposed mechanism achieves a significant resolution improvement with better resolution insensitivity to the process and temperature variations.

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Section: Conventional Pulse-shrinking Mechanismmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Chen¹,

Chen²,

You³

et al. 2017

dtetr

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show abstract

“…A pulse-shrinking (PS) TDC shown in Fig. 8(b), which is also a type of Vernier TDCs, utilizes the delay difference between rising and falling transitions of a buffer [19,20]. The buffer is intentionally designed to have different rise and fall delays, e.g.…”

Section: Time-to-digital Convertersmentioning

confidence: 99%

Time-domain approach for analog circuits in deep sub-micron LSI

Asada

Nakura²,

Iizuka

et al. 2018

IEICE Electron. Express

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As the scaling of LSI is going to extremely fine regions toward the ultimate feature size, one of difficulties faced in analog circuit design is reduction of the dynamic range (DR) due to the supply voltage reduction. Unlike digital circuits, where the noise margin for logic operation is the key criterion, analog circuits need an enough DR. The reduced supply voltage directly results in DR degradation of the conventional analog circuits in the voltage-domain. Especially in mixed-signal LSIs, supply voltage instability, caused by logic operation, tends to degrade DR further. In this paper, we will first discuss potential capability of a new paradigm of time-domain circuits by comparing with the conventional voltage/current-domain circuits in terms of DR and power consumption. Next, as basic circuit components for the time-domain approach, current status of TDA (Time-Difference Amplifier) and TDC (Time-to-Digital Converter) will be reviewed. Finally, some application examples of the time-domain circuits are introduced to demonstrate the feasibility of the time-domain approach.

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“…Moreover, changing the capacitors values every single cycle is problematic as the values of the capacitors need to settle down, which requires extra time and hence, reduces the effective throughput that the TDC can reach. Other TDC architectures can be found in the literature including pulse shrinking (Liu et al, 2007;Chen et al, 2000) and time amplification techniques (Safi-Harb and Roberts, 2006;Oulmane and Roberts, 2004;Chao and Chang, 2009) …”

Section: Introductionmentioning

confidence: 99%

A programmable multi-step cyclic Vernier time-to-digital converter

Raymond¹,

Ghoneima²,

Ismail³

2013

IJCAD

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Abstract:A new architecture for a time-to-digital converter (TDC) is presented in this paper. The programmability feature of the new proposed architecture allows for the reusability of the design for various applications requiring different resolution, throughput, area and power constraints. One of the main motives behind this work (besides the programmability feature) is trying to resolve the inherent TDC design tradeoffs between resolution, throughput and complexity. The new TDC was implemented using the TSMC 65 nm technology. A detailed transistor level design along with the system level analysis is presented. For a reliable operation, a new auto calibration scheme is proposed that guarantees the successful operation of the system. Simulation results show the successful operation of the proposed TDC and its ability to auto calibrate itself for any process corner. As an example, for a resolution of 4 ps with an input range of 1 ns, the proposed TDC had a throughput of 45 MS/s while maintaining a DNL of 0.85 LSB and INL of 0.93 LSB.Keywords: time measurement; time-to-digital converters; TDC; data conversion; calibration systems.Reference to this paper should be made as follows: Raymond, M., Ghoneima, M. and Ismail, Y. (2013) 'A programmable multi-step cyclic Vernier time-to-digital converter', Int.

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A CMOS pulse-shrinking delay element for time interval measurement

Cited by 154 publications

References 8 publications

A CMOS Pulse-Shrinking Mechanism with Improved Resolution

A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Time-domain approach for analog circuits in deep sub-micron LSI

A programmable multi-step cyclic Vernier time-to-digital converter

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