A CMOS SPDT RF Switch with 68 dB Isolation and 1.0 dB Loss Feathering Switched Resonance Network for MIMO Applications

Fu, Xi; Wang, Yun; Li, Zheng; Shirane, Atsushi; Okada, Kei

doi:10.1587/transele.2020cdp0004

Cited by 5 publications

(3 citation statements)

References 26 publications

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“…As the gate width increases, the OFF-capacitance C off increases proportionally, while the ON-resistor R on decreases inversely. A small R on results in a low IL, but a large C off degrades the isolation [26]. In this design, the gate width is set to 76.8 μm to achieve low IL.…”

Section: ) 5-bit Binary-weighted Transistor Arraymentioning

confidence: 99%

“…The two 4-GHz IF signals are connected to separate output ports since they have different phases.1) RF DPDT Switch: Fig.16shows the detailed circuit diagram of the RF DPDT switch. The switched parallel resonance network topology[26] is utilized to reduce the IL. To connect the input port IN1 to the output port OUT1, MOS transistors M 2 and M 4 turn off and M 1 and M 3 turn on.…”

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confidence: 99%

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A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer

Ide

Shirane

Yanagisawa

et al. 2022

IEEE J. Solid-State Circuits

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This article introduces a wirelessly powered phasedarray transceiver for fifth-generation (5G) relay systems. To realize the battery-less relay operation, 24-GHz wireless power transfer (WPT) is employed. This relay transceiver consists of the proposed vector-summing backscatter for Transmitter (Tx) and a passive phase-shifting self-heterodyne Receiver (Rx) with a rectifier for Rx and WPT. The receiver generates dc power from the 24-GHz WPT signal, which is also used as a local oscillator (LO) signal to down-convert the 28-GHz 5G modulated data to a 4-GHz IF. The vector-summing backscatter up-converts the 4-GHz IF signal to 28-GHz using a 24-GHz LO signal while working as a 360 • phase shifter with a 7-bit resolution. Both transmitter and receiver operate only using the generated power from the 24-GHz WPT. The chip area of the eight-path transceiver is 1.8 mm 2 and the transceiver is mounted on a 32-element phased-array antenna board. This module generates 3.1-mW dc power from 6.7-mW/cm 2 received power density at 24 GHz. The transmitter achieves a −2.2-dBm measured saturated equivalent isotropically radiated power (EIRP) and supports a −30 • to +30 • beam range. The measured error vector magnitude (EVM) values are −27.5 dB for Tx mode and −31.3 dB for Rx mode with a 400-MHz 64-QAM orthogonal frequency division multiple access (OFDMA)-mode signal (5G new radio (NR), MCS 19). The power consumption for each path is 0.03 mW in both Tx and Rx modes.

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Section: ) 5-bit Binary-weighted Transistor Arraymentioning

confidence: 99%

mentioning

confidence: 99%

A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer

Ide

Shirane

Yanagisawa

et al. 2022

IEEE J. Solid-State Circuits

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“…However, both GaAs and SOS technologies need expensive substrate and extra CMOS-based digital circuits. Although standard bulk CMOS technology provides good system integration capability [13], it suffers from poor linearity and high IL due to RF coupling through the lossy substrate and parasitic effects [14,15,16,17,18]. Because of high integration capability, low parasitic capacitance, and low substrate losses, SOI CMOS technology is proved to be an excellent candidate for switch design [19,20,21,22].…”

Section: Introductionmentioning

confidence: 99%

A high-linearity SP5T SOI switch with a resistive biasing network and capacitance & resistor compensation technology

Zhang,

Ma,

et al. 2024

IEICE Electron. Express

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This letter presents a high-linearity single-pole five-throw switch implemented in a 0.13-μm silicon-on-insulator (SOI) CMOS process. In order to improve the linearity of switch, the uniform voltage division across the stacked-FETs is obtained by the proposed structure, which employs a resistive biasing network as well as compensation technology of drain-to-source capacitance and DC balance resistor. The measured input 0.1 dB compression point of the proposed switch is 42 dBm. Insertion losses are 0.38 dB and 0.5 dB for TX and RX modes at 0.9 GHz. The switch exhibits a second harmonic of -91 dBc, and third harmonic power of -84 dBc with a +28 dBm input power at 0.9 GHz.

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A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation

Fu,

You,

Wang

et al. 2024

IEEE J. Solid-State Circuits

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A CMOS SPDT RF Switch with 68 dB Isolation and 1.0 dB Loss Feathering Switched Resonance Network for MIMO Applications

Cited by 5 publications

References 26 publications

A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer

A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer

A high-linearity SP5T SOI switch with a resistive biasing network and capacitance & resistor compensation technology

A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation

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