A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method

Mantyniemi, A.; Rahkonen, Timo; Kostamovaara, J.

doi:10.1109/jssc.2009.2032260

Cited by 136 publications

(65 citation statements)

References 46 publications

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“…Using a binary search algorithm in determining time elapsed between two pulses allows for a measurement time that is much less dependent on the required resolution. However, using the implementation presented in Mantyniemi et al (2009), the value of the MOS capacitors bank needs to be changed every single cycle for ten cycles. To preserve the required resolution and accuracy, the capacitors should be allowed some time (~ 7 ns) for its value to settle down which again decreases the practical throughput of the TDC.…”

Section: Throughput Versus Complexitymentioning

confidence: 99%

“…The second problem with the cyclic Vernier TDC is that its input range is controlled by the value of T S , which in turn affects the measurement time as shown in equation (5). In an attempt to decouple the resolution and measurement time dependency, the successive approximation TDC was introduced (Mantyniemi et al, 2009). The topology which uses a binary search algorithm in its operation provides a constant measurement time for a given input range for a given setup.…”

Section: Introductionmentioning

confidence: 99%

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A programmable multi-step cyclic Vernier time-to-digital converter

Raymond¹,

Ghoneima²,

Ismail³

2013

IJCAD

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Abstract:A new architecture for a time-to-digital converter (TDC) is presented in this paper. The programmability feature of the new proposed architecture allows for the reusability of the design for various applications requiring different resolution, throughput, area and power constraints. One of the main motives behind this work (besides the programmability feature) is trying to resolve the inherent TDC design tradeoffs between resolution, throughput and complexity. The new TDC was implemented using the TSMC 65 nm technology. A detailed transistor level design along with the system level analysis is presented. For a reliable operation, a new auto calibration scheme is proposed that guarantees the successful operation of the system. Simulation results show the successful operation of the proposed TDC and its ability to auto calibrate itself for any process corner. As an example, for a resolution of 4 ps with an input range of 1 ns, the proposed TDC had a throughput of 45 MS/s while maintaining a DNL of 0.85 LSB and INL of 0.93 LSB.Keywords: time measurement; time-to-digital converters; TDC; data conversion; calibration systems.Reference to this paper should be made as follows: Raymond, M., Ghoneima, M. and Ismail, Y. (2013) 'A programmable multi-step cyclic Vernier time-to-digital converter', Int.

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Section: Throughput Versus Complexitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A programmable multi-step cyclic Vernier time-to-digital converter

Raymond¹,

Ghoneima²,

Ismail³

2013

IJCAD

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“…In general, the Time to Digital Converter (TDC) is implemented in programmable structures FPGA or CPLD and ASIC. Of course, better system performance is obtained by using ASICs [6,7] than FPGAs, but for a prototype small series of FPGA structures are used. This is done because one can easily modify the system and its operation at the designing process.…”

Section: Introductionmentioning

confidence: 99%

High Resolution Time-Interval Measurement Systems Applied to Flow Measurement

Grzelak¹,

Kowalski²,

Czoków³

et al. 2014

Metrology and Measurement Systems

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The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.

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“…However this resolution is sometimes not enough for a precise analog signal processing required to find 1 ps time resolution. Some TDCs realized sub-gate delay resolution by the Vernier delay line [1], interpolation [2] and a delay line with local passive interpolation [3], however, it is difficult to realize 1 ps resolution with small area and simple processing. Then, time difference amplifiers (TDA) [4,5,6] are an innovative method to improve the time resolution as well as the evolution of the ADCs.…”

Section: Introductionmentioning

confidence: 99%

A 8bit two stage time-to-digital converter using time difference amplifier

Mandai¹,

Nakura

Ikeda

et al. 2010

IEICE Electron. Express

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Abstract:We propose a 8 bit two stage time-to-digital converter (TDC) using a time difference amplifier. The time resolution is 1.89 ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation assuming the standard 0.18 um CMOS. To amplify the time residue of the first stage, the 16x cascaded time difference amplifier (TDA) using differential logic delay cells is employed. Time resolution of the proposed TDC becomes finer by employing the 16x cascaded TDA and the linearity is improved by using only one TDA in the two stage TDC instead of using a lot of TDAs.

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A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method

Cited by 136 publications

References 46 publications

A programmable multi-step cyclic Vernier time-to-digital converter

A programmable multi-step cyclic Vernier time-to-digital converter

High Resolution Time-Interval Measurement Systems Applied to Flow Measurement

A 8bit two stage time-to-digital converter using time difference amplifier

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