2006 American Control Conference 2006
DOI: 10.1109/acc.2006.1656499
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A co-processor FPGA platform for the implementation of real-time model predictive control

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Cited by 65 publications
(46 citation statements)
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“…This paper is concerned with facilitating applications of MPC in which computational complexity, in particular computation time, is likely to be an issue. One can foresee that applications to embedded systems, with the MPC algorithm implemented in a chip or an FPGA [5,13,14,17], are likely to run up against this problem.…”
Section: The Basic Ideamentioning
confidence: 99%
“…This paper is concerned with facilitating applications of MPC in which computational complexity, in particular computation time, is likely to be an issue. One can foresee that applications to embedded systems, with the MPC algorithm implemented in a chip or an FPGA [5,13,14,17], are likely to run up against this problem.…”
Section: The Basic Ideamentioning
confidence: 99%
“…This has prompted a number of researchers to investigate means for increasing the speed with which optimal controls can be computed. Much of this work has focused on improving the algorithms [1], [11].…”
Section: Related Work a Control Backgroundmentioning
confidence: 99%
“…[24] addressed the implementation of MPC on very resource-constrained embedded systems with an FPGA implementation consisting of a soft-core processor attached to a co-processor used to accelerate computations that allowed data reuse. [23] also proposed a mixed software-hardware implementation where the core matrix computations are implemented in parallel custom hardware, whereas the remaining operations are implemented on a soft-processor core synthesized into the FPGA. The computational bottlenecks in implementing a logarithmic-barrier method for solving an unstructured QP were identified for determining which computations should be carried out in which unit.…”
Section: Related Workmentioning
confidence: 99%