A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers

Xu, Xizhen; Ziavras, Sotirios G.

doi:10.1093/ietisy/e89-d.2.639

Cited by 2 publications

(2 citation statements)

References 18 publications

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“…Many different researches for the implementation of 2D FFT algorithms on FPGA have been proposed since the introduction of this technology. For example, XU et al [10] proposed an FPGA-based reconfigurable, hierarchical-SIMD (H-SIMD) machine with its co-design of the Pyramidal Instruction Set Architecture (PISA). He assumes a multiple FPGA board where each FPGA is configured as a separated SIMD machine to implement 2D FFT.…”

Section: Background and Related Workmentioning

confidence: 99%

FPGA based Reconfigurable 2D FFT System

Al-Allaf¹,

Dawwd²

2011

(AREJ)

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This paper develops a system level architecture for implementing a cost-efficient, FPGA-based reconfigurable two dimensional (2D) FFT system. The adopted approach considers both the hardware cost (in terms of FPGA resource requirements), and performance (in terms of throughput). These two extremes are optimized based on using run time reconfiguration, double buffering technique, shared Dual Ported RAM (DPRAM) modules and the "hardware virtualization" to reuse the available processing components. The system employs two one Dimensional (1D) FFT processor each with sixteen reconfigurable parallel FFT cores. Each core represents a 16 complex point parallel FFT engine. Thus the architecture supports transform length of 256X256 complex points, as a demonstrator to the design idea, using fixed-point arithmetic and has been developed using radix-4 butterfly architecture. The simulation results that have been performed using VHDL modeling language and ModelSim software shows that the full design can be implemented using single FPGA platform requiring about 50,000 Slices.

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Section: Background and Related Workmentioning

confidence: 99%

FPGA based Reconfigurable 2D FFT System

Al-Allaf¹,

Dawwd²

2011

(AREJ)

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“…The capabilities of FPGAs have recently improved tremendously [15][16][17] so they are now frequently used by NID systems. Sidhu et al [4] proposed a straightforward algorithm to construct non-deterministic finite automata (NFA) representing given regular expressions.…”

Section: Related Workmentioning

confidence: 99%

Efficient hardware support for pattern matching in network intrusion detection

Guinde

Ziavras

2010

Computers & Security

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Abstract-Deep packet inspection forms the backbone of any Network Intrusion Detection (NID) system. It involves matching known malicious patterns against the incoming traffic payload. Pattern matching in software is prohibitively slow in comparison to current network speeds. Due to the high complexity of matching, only FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit) platforms can provide efficient solutions. FPGAs facilitate target architecture specialization due to their field programmability. Costly ASIC designs, on the other hand, are normally resilient to pattern updates. Our FPGA-based solution performs high-speed pattern matching while permitting pattern updates without resource reconfiguration. To its advantage, our solution can be adopted by software and ASIC realizations, however at the expense of much lower performance and higher price, respectively. Our solution permits the NID system to function while pattern updates occur. An off-line optimization method first finds common subpatterns across all the patterns in the SNORT database of signatures [14]. A novel technique then compresses each pattern into a bit vector, where each bit represents such a sub-pattern. This approach reduces drastically the required on-chip storage as well as the complexity of pattern matching. The bit vectors for newly discovered patterns can be generated easily using a simple high-level language program before storing them into the on-chip RAM. Compared to earlier approaches, not only is our strategy very efficient while supporting runtime updates but it also results in impressive area savings; it utilizes just 0.052 logic cells for processing and 17.77 bits for storage per character in the current SNORT database of 6455 patterns. Also, the total number of logic cells for processing the traffic payload does not change with pattern updates.

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A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers

Cited by 2 publications

References 18 publications

FPGA based Reconfigurable 2D FFT System

FPGA based Reconfigurable 2D FFT System

Efficient hardware support for pattern matching in network intrusion detection

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