A code compression system based on pipelined interpreters

Hoogerbrugge, Jan; Augusteijn, Lex; Trum, Jeroen; Wiel, Rik van de

doi:10.1002/(sici)1097-024x(199909)29:11<1005::aid-spe270>3.0.co;2-f

Cited by 42 publications

(40 citation statements)

References 16 publications

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“…J Hoogerbrugge and L Augusteijn [17], [18] have proposed that software pipelining interpreters is a way to reduce dispatch branch cost on architectures with split indirect branches. In addition, Subroutine threading [19] has also been proposed to avoid the overheads of indirect branches in intrepreter implementations.…”

Section: Related Workmentioning

confidence: 99%

Performance Research and Optimization on CPython’s Interpreter

Cao¹,

Gu²,

Ren³

et al. 2015

Annals of Computer Science and Information Systems

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Abstract-In this paper, the performance research on CPython's latest interpreter is presented, concluding that bytecode dispatching takes about 25 percent of total execution time on average. Based on this observation, a novel bytecode dispatching mechanism is proposed to reduce the time spent on this phase to a minimum. With this mechanism, the blocks associated with each kind of bytecodes are rewritten in hand-tuned assembly, their opcodes are renumbered, and their memory spaces are rescheduled. With these preparations, this new bytecode dispatching mechanism replaces the time-consuming memory reading operations with rapid operations on registers.This mechanism is implemented in CPython-3.3.0. Experiments on lots of benchmarks demonstrate its correctness and efficiency. The comparison between original CPython and optimized CPython shows that this new mechanism achieves about 8.5 percent performance improvement on average. For some particular benchmarks, the maximum improvement is up to 18 percentages.

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Section: Related Workmentioning

confidence: 99%

Performance Research and Optimization on CPython’s Interpreter

Cao¹,

Gu²,

Ren³

et al. 2015

Annals of Computer Science and Information Systems

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“…Ertl and Gregg [7] showed that interpreters (especially those using switch dispatch) spend most of their time in branch mispredictions on modern desktop architectures. Interpreter software pipelining [14] is a valuable technique for architectures with delayed branches (e.g. Philips Trimedia) or prepare to branch instructions (e.g.…”

Section: Related Workmentioning

confidence: 99%

The case for virtual register machines

Davis

Beatty

Casey

et al. 2003

Proceedings of the 2003 Workshop on Interpreters, Virtual Machines and Emulators

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Virtual machines (VMs) are a popular target for language implementers. A longrunning question in the design of virtual machines has been whether stack or register architectures can be implemented more efficiently with an interpreter. Many designers favour stack architectures since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly. In this paper, we present a working system for translating stackbased Java virtual machine (JVM) code to a simple register code. We describe the translation process, the complicated parts of the JVM which make translation more difficult, and the optimisations needed to eliminate copy instructions. Experimental results show that a register format reduced the number of executed instructions by 34.88%, while increasing the number of bytecode loads by an average of 44.81%. Overall, this corresponds to an increase of 2.32 loads for each dispatch removed. We believe that the high cost of dispatches makes register machines attractive even at the cost of increased loads.

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“…Some researchers [12,24,9] have shown the virtues of reducing code size, without decompression before execution, by using bytecode interpreters tailored for one program. Compression of the bytecode, capable of direct execution without decompression, would further reduce code size.…”

Section: Introductionmentioning

confidence: 99%

“…In that case, a virtual machine tailored for the program can be used to reduce space. This is the approach taken in [12,24,9]. Further code size reduction can be obtained with a compression of the virtual instructions.…”

Section: Introductionmentioning

confidence: 99%

Generation of fast interpreters for Huffman compressed bytecode

Latendresse

Feeley

2003

Proceedings of the 2003 Workshop on Interpreters, Virtual Machines and Emulators

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Embedded systems often have severe memory constraints requiring careful encoding of programs. For example, smart cards have on the order of 1K of RAM, 16K of non-volatile memory, and 24K of ROM. A virtual machine can be an effective approach to obtain compact programs but instructions are commonly encoded using one byte for the opcode and multiple bytes for the operands, which can be wasteful and thus limit the size of programs runnable on embedded systems. Our approach uses canonical Huffman codes to generate compact opcodes with customsized operand fields and with a virtual machine that directly executes this compact code. We present techniques to automatically generate the new instruction formats and the decoder. In effect, this automatically creates both an instruction set for a customized virtual machine and an implementation of that machine. We demonstrate that, without prior decompression, fast decoding of these virtual compressed instructions is feasible. Through experiments on Scheme and Java, we demonstrate the speed of these decoders. Java benchmarks show an average execution slowdown of 9%. The reductions in size highly depend on the original bytecode and the training samples, but typically vary from 40% to 60%.

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A code compression system based on pipelined interpreters

Cited by 42 publications

References 16 publications

Performance Research and Optimization on CPython’s Interpreter

Performance Research and Optimization on CPython’s Interpreter

The case for virtual register machines

Generation of fast interpreters for Huffman compressed bytecode

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