A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems

Lu, Yi; Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

doi:10.1109/fccm.2010.18

Cited by 20 publications

(17 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This information is critical in finding the potential memory access related bottlenecks when the application is executed on a particular heterogeneous reconfigurable architecture; • the discovery of the exact timing and activity span (starting and ending points of a kernel execution). The extracted information is required for task scheduling and mapping on reconfigurable systems [29]; • the identification of the main phases in the application based on the activity spans of the kernels. The kernels that are active at the same time interval are possibly relevant (communicating).…”

Section: B Experimental Analysismentioning

confidence: 99%

tQUAD - Memory Bandwidth Usage Analysis

Ostadzadeh

Corina

Galuzzi

et al. 2010

2010 39th International Conference on Parallel Processing Workshops

Self Cite

View full text Add to dashboard Cite

One of the main issues in heterogeneous reconfigurable computing is the well-known processor/memory bottleneck. Due to the memory bandwidth limitations, the performance of execution of an application can dramatically increase via the efficient usage of the memory. In this paper, we present tQUAD, a new tool for the memory bandwidth usage analysis. This tool is capable of delivering detailed temporal memory bandwidth usage information for the functions in an application throughout a comprehensive analysis of the memory access patterns of individual functions. This tool, first in its kind, provides an accurate analysis of the task execution and memory bandwidth usage which in the end leads to a sophisticated partitioning of the tasks into different phases during the execution span of an application. Together with an accurate description of the tool, the paper presents a real case study from the multimedia domain to detail all features of the proposed tool.

show abstract

Section: B Experimental Analysismentioning

confidence: 99%

tQUAD - Memory Bandwidth Usage Analysis

Ostadzadeh

Corina

Galuzzi

et al. 2010

2010 39th International Conference on Parallel Processing Workshops

Self Cite

View full text Add to dashboard Cite

show abstract

“…Other hand, diverse set of resources interconnected with a high speed networks provides a new computing platform [20] [21] called Heterogeneous Computing System, which could support executing computationally intensive parallel and distributed applications. An emerging computing platform which integrates the array of programmable logic resources and soft core processors together on a single chip [15] [16] [17] [18] called Heterogeneous Reconfigurable Computing Systems (HRCS). The HRCS platform is an emerging paradigm of research that offers cost effective solutions for computationally intensive applications through hardware reuse and many multimedia applications [2] were accelerated by HRCS.…”

Section: Introductionmentioning

confidence: 99%

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

Vucha¹,

Rajawat²

2014

IJESA

View full text Add to dashboard Cite

show abstract

“…Marconi et al were inspired by [1] and presented a novel 3D total contiguous surface heuristic in order to equip the scheduler with "blockingawareness" capability [2]. Subsequently, Lu et al created the first scheduling algorithm that considers the data dependencies and communication amongst hardware tasks, and between tasks and external devices [3]. Efficient placement and free space management algorithms are equally important.…”

Section: Related Workmentioning

confidence: 99%

Hardware Task Scheduling for Partially Reconfigurable FPGAs

Charitopoulos

Koidis

Papadimitriou

et al. 2015

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems, swapping in and out HW tasks. To coordinate the on-demand task execution, we propose and implement a run time system manager for scheduling software (SW) tasks on available processor(s) and hardware (HW) tasks on any number of reconfigurable regions of a partially reconfigurable FPGA. Fed with the initial partitioning of the application into tasks, the corresponding task graph, and the available task mappings, the RTSM considers the runtime status of each task and region, e.g. busy, idle, scheduled for reconfiguration/execution etc., to execute tasks. Our RTSM supports task reuse and configuration prefetching to minimize reconfigurations, task movement among regions to efficiently manage the FPGA area, and RR reservation for future reconfiguration and execution. We validate its correctness using our RTSM to execute an image processing application on a ZedBoard platform. We also evaluate its features within a simulation framework, and find that despite the technology limitations, our approach can give promising results in terms of quality of scheduling. IntroductionReconfiguration can dynamically adapt the functionality of hardware systems by swapping in and out HW tasks. To select the proper resource for loading and triggering HW task reconfiguration and execution in partially reconfigurable systems with FPGAs, efficient and flexible runtime system support is needed [6]. In this paper we propose and implement a Run-Time System Manager (RTSM) incorporating efficient scheduling mechanisms that balance effectively the execution of HW and SW tasks and the use of physical resources. We aim to execute as fast as possible a given application, without exhausting the physical resources. Our motivation during the development of RTSM was to find ways to overcome the strict technology restrictions imposed by the Xilinx PR flow [8]:  Static partitioning of the reconfigurable surface in reconfigurable regions (RR).

show abstract

A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems

Cited by 20 publications

References 7 publications

tQUAD - Memory Bandwidth Usage Analysis

tQUAD - Memory Bandwidth Usage Analysis

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems

Hardware Task Scheduling for Partially Reconfigurable FPGAs

Contact Info

Product

Resources

About