A communication characterisation of Splash-2 and Parsec

Barrow-Williams, Nick; Fensch, Christian; Moore, Simon W.

doi:10.1109/iiswc.2009.5306792

Cited by 166 publications

(121 citation statements)

References 15 publications

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“…We utilized the Parsec benchmarks [10] with 'simsmall' input data run with 32 cores (arranged in a 8 × 4 mesh), the maximum available in our configuration. As discussed in [7] the spatial patterns of the application composing this benchmark suite do not present any noticeable 'hot spot'. We will see later that this may happen with the transactional memory applications.…”

Section: B Directory-based Cache Coherencymentioning

confidence: 99%

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Navaridas

Khan

et al. 2012

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

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Abstract-Architectural simulation is an essential tool when it comes to evaluating the design of future many-core chips. However, reproducing all the components of such complex systems precisely would require unreasonable amounts of computing power. Hence, a trade off between accuracy and compute time is needed. For this reason most state-of-the-art tools do not have accurate models for the networks-on-chip, and rely on timing models that permit fast-simulation. Generally, these models are very simplistic and disregard contention for the use of network resources. As the number of nodes in the network-on-chip grows, fluctuations with contention and other parameters can considerably affect the accuracy of such models. In this paper we present and evaluate a collection of timing models based on a reservation scheme which consider the contention for the use of network resources. These models provide results quickly while being more accurate than simple no-contention approaches.

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Section: B Directory-based Cache Coherencymentioning

confidence: 99%

Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Navaridas

Khan

et al. 2012

2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip

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“…Their work requires the generation of memory traces to guide data mapping for future executions of the applications, which may lead to a high overhead [3]. A similar technique is used in Marathe and Mueller [17] to perform data mapping dynamically.…”

Section: Related Workmentioning

confidence: 99%

“…For the random mapping, we randomly generated a thread and data mapping for each execution. For the Oracle mapping, we generated traces of all memory accesses for each application and performed an analysis of the sharing and page usage patterns, similar to [3]. Autopin was executed with 5 mappings: the Oracle mapping and 4 random mappings.…”

Section: Comparison To Related Workmentioning

confidence: 99%

A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures

Cruz

Diener

Pilla

et al. 2016

Euro-Par 2016: Parallel Processing

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Abstract. In modern shared-memory architectures, it is important to map threads and data in a way that increases the locality of their memory accesses, thereby improving performance and energy efficiency. Threads that access shared data should be mapped close to each other in the memory hierarchy, while the data they access should be mapped to their NUMA node, which is called sharing-aware mapping. In this paper, we propose SAMMU, which adds sharing-awareness to the memory management unit in current architectures. SAMMU analyzes the memory access behavior in hardware and provides information to the operating system so it can perform an online mapping of threads and data. In the evaluation with a wide range of parallel applications, performance was improved by up to 35.7% (13.1% on average).

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“…Further, the overhead of communication between threads is often reduced, because of improved physical proximity between processing elements. For example, Barrow-Williams et al [10] use a 10-cycle latency for shared L2 cache access in their characterization of communication patterns of parallel benchmarks on modern multicore architectures.…”

Section: Changing Cost Modelsmentioning

confidence: 99%