2018 IEEE Custom Integrated Circuits Conference (CICC) 2018
DOI: 10.1109/cicc.2018.8357012
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A compact 2.4GHz polar/quadrature reconfigurable digital power amplifier in 28nm logic LP CMOS

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Cited by 4 publications
(3 citation statements)
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“…η avg represents the average drain efficiency of DPA. (7) shows the effect of the number of LO phases on the HB-TX average efficiency. Besides, the LO duty cycle of the transmitter also affects the efficiency.…”
Section: B Mathematical Model For Efficiency Analysismentioning
confidence: 99%
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“…η avg represents the average drain efficiency of DPA. (7) shows the effect of the number of LO phases on the HB-TX average efficiency. Besides, the LO duty cycle of the transmitter also affects the efficiency.…”
Section: B Mathematical Model For Efficiency Analysismentioning
confidence: 99%
“…As shown in Fig. 6, timing A employed in (7) and timing B employed in (8) are defined. The LO with 25% duty cycle decreases the leakage current in DPA cells so the efficiency with timing B is improved.…”
Section: B Mathematical Model For Efficiency Analysismentioning
confidence: 99%
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