A compact 213 GHz CMOS fundamental oscillator with 0.56 mW output power and 3.9% efficiency using a capacitive transformer

Wang, Hao; Kuzmenko, Daniel; Yu, Bo; Ye, Yu; Gu, Jane; Rashtian, Hooman; Liu, Xiaoguang

doi:10.1109/mwsym.2017.8058972

Cited by 5 publications

(2 citation statements)

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“…where k is an arbitrary integer. Both equations have been used recently to design high-efficiency millimeter-wave oscillators [12], [13], [15], [29]. Once A opt is determined for a certain transistor and bias condition, the embedding network can be synthesized.…”

Section: A Review Of Existing Approaches To Maximizing Oscillatormentioning

confidence: 99%

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High-Efficiency Millimeter-Wave Single-Ended and Differential Fundamental Oscillators in CMOS

Wang

Chen

et al. 2018

IEEE J. Solid-State Circuits

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This paper reports an approach to designing compact high efficiency millimeter-wave fundamental oscillators operating above the fmax/2 of the active device. The approach takes full consideration of the nonlinearity of the active device and the finite quality factor of the passive devices to provide an accurate and optimal oscillator design in terms of the output power and efficiency. The 213-GHz single-ended and differential fundamental oscillators in 65-nm CMOS technology are presented to demonstrate the effectiveness of the proposed method. Using a compact capacitive transformer design, the single-ended oscillator achieves 0.79-mW output power per transistor (16 µm) at 1.0-V supply and a peak dc-to-RF efficiency of 8.02% (VDD=0.80 V) within a core area of 0.0101 mm 2 , and the measured phase noise is −93.4 dBc/Hz at 1-MHz offset. The differential oscillator exhibits approximately the same performance. A 213-GHz fundamental voltage-controlled oscillator (VCO) with bulk tuning method is also developed in this work. The measured peak efficiency of the VCO is 6.02% with a tuning rang of 2.3% at 0.6-V supply.

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Section: A Review Of Existing Approaches To Maximizing Oscillatormentioning

confidence: 99%

“…Note that we take advantage of the parallel connection between R 1 and C 1 , and utilize a capacitive transformer to match a typical system impedance of 50 Ω to the calculated optimum load, as shown in Fig. 8(b) [29].…”

Section: A Process and Transistormentioning

confidence: 99%