A compact 31-input programmable majority gate based on capacitive threshold logic

Leblebici, Yusuf; Gürkaynak, Frank K.; Mlynek, D.

doi:10.1109/iscas.1998.706852

Cited by 14 publications

(10 citation statements)

References 7 publications

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“…Experimental results from different CTL gates fabricated in standard CMOS technology [56]- [58], [60] have shown the proper functionality of this type of TLG and its large fan-in capability (gates with fan-in have been simulated). This later feature is due to the auto-offset cancellation technique widely used in chopper-type CMOS comparators.…”

Section: A Switched Capacitormentioning

confidence: 99%

“…This later feature is due to the auto-offset cancellation technique widely used in chopper-type CMOS comparators. Originally, CTL gates required a double-poly process, but some developments (such as dynamic and differential CTL [56]) use the MOS cap with a small penalty on the fan-in fan-in . CTL gates have a simple regular structure and are able to implement large fan-ins, while their main drawbacks are large delays, large area, dc power consumption, and the threshold value programming mechanism.…”

Section: A Switched Capacitormentioning

confidence: 99%

“…In addition, each CTL gate may require a different reference voltage; thus, it is very difficult if not impossible to build circuits with a large number of CTL gates. This problem is solved by the improved CTL gate [56], which operates exclusively with binary input logic levels. Another solution to this problem is the CP-CTL [61], [62], which does not rely on the presence of additional external voltages.…”

Section: A Switched Capacitormentioning

confidence: 99%

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VLSI implementations of threshold logic- a comprehensive survey

Beiu

Quintana

Avedillo

2003

IEEE Trans. Neural Netw.

196

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This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

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Section: A Switched Capacitormentioning

confidence: 99%

Section: A Switched Capacitormentioning

confidence: 99%

Section: A Switched Capacitormentioning

confidence: 99%

See 1 more Smart Citation

VLSI implementations of threshold logic- a comprehensive survey

Beiu

Quintana

Avedillo

2003

IEEE Trans. Neural Netw.

196

View full text Add to dashboard Cite

show abstract

“…The overall circuit complexity increases linearly both with maximum window size (m) and with word length (n). 5. The clock frequency is essentially independent of the input window size (m), and the overall latency of the pipeline is (n-1) clock cycles.…”

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confidence: 99%

A Modular and Scalable Architecture for the Realization of High‐speed Programmable Rank Order Filters Using Threshold Logic

1999

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We present a new scalable architecture for the realization of fully programmable rank order filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The CTL-based realization of the majority gates used in the ROF architecture allows the filter rank as well as the window size to be user-programmable, using a much smaller silicon area, compared to conventional realizations of digital median filters. The proposed filter architecture is completely modular and scalable, and the circuit complexity grows only linearly with maximum window size (m) and with word length (n). A prototype of the proposed filter circuit has been designed and fabricated using double-polysilicon 0.8 μm CMOS technology. Detailed post-layout simulations and test results of the ROF prototype circuit indicate that the new architecture can accommodate sampling clock rates of up to 50 MHz, corresponding to an effective data processing rate of 800 Mb/s for a very large filter with window size 63 and word length of 16 bits.

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“…The word-length dictates the number of the majority decision gates, whereas the window size determines the number of ROF-cells driving one of these majority gates. The programmable majority decision gates are realized using the capacitive threshold logic (CTL) circuit architecture presented earlier [5]. This allows simple implementation of programmable majority gates with up to 63 parallel inputs, using a very small silicon area (625 m x 130 m for 63-bit majority gate).…”

Section: Implementation Of the Programmable Rof Architecturementioning

confidence: 99%

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering

Hatirnaz

Gürkaynak

Leblebici

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No

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A new modular architecture is presented for the realization of high-speed binary sorting engines, based on efficient rank ordering. Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The overall complexity of the proposed bitserial architecture increases linearly with the number of input vectors to be sorted (window size = m) and with the bitlength of the input vectors (word size = n), and the sorter architecture can be easily expanded to accommodate large vector sets. Detailed simulations indicate that the sorter structure can operate at sampling clock rates of up to 50 MHz, where the throughput is boosted by fine-grain pipelining. It is demonstrated that the proposed sorting engine is capable of producing a fully sorted output vector set in (m+n-1) clock cycles, i.e., in linear time.

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A compact 31-input programmable majority gate based on capacitive threshold logic

Cited by 14 publications

References 7 publications

VLSI implementations of threshold logic- a comprehensive survey

VLSI implementations of threshold logic- a comprehensive survey

A Modular and Scalable Architecture for the Realization of High‐speed Programmable Rank Order Filters Using Threshold Logic

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering

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