A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration

Wan, Jing; Royer, C. Le; Zaslavsky, Alexander; Cristoloveanu, S.

doi:10.1109/led.2011.2176908

Cited by 113 publications

(81 citation statements)

References 10 publications

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“…Among other uses such as ESD [1], the Z 2 -FET or similar structures, can be considered as a promising candidate to operate as single-transistor DRAM cell [2], [3]. In order to succeed, 1T-DRAM cells need to comply with several requirements [4]: i) low operating voltage and power consumption, ii) long retention time, iii) high density integration, iv) fast random access, and v) easy fabrication.…”

Section: Introductionmentioning

confidence: 99%

Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Navarro

Lacord

Parihar

et al. 2017

IEEE Trans. Electron Devices

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Abstract-The Z 2 -FET operation as capacitor-less DRAM is analyzed using advanced 2D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28 nm FD-SOI devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z 2 -FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.

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Section: Introductionmentioning

confidence: 99%

Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Navarro

Lacord

Parihar

et al. 2017

IEEE Trans. Electron Devices

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“…Therefore, the search for a DRAM substitute is gaining momentum. The main focus is on capacitorless approaches [4,5].…”

Section: Introductionmentioning

confidence: 99%

Simulation of Capacitorless Memory Cell Based on GaN/AlGaN/GaN heterostructures

Chattopadhyay¹,

Rajkamal²,

Sharma³

et al. 2014

J. Phys. Chem. Mater.

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Abstract:Present work investigates the conditions for simultaneous presence of 2DEG and 2DHG in GaN/AlGaN/GaN layer structure using TCAD. The possible application of this structure as a capacitorless memory element is explored. The 2DHG is located closer to the gate. Therefore it shields the 2DEG, which is located farther away from the gate. The spacer regions between the gate and source/ drain in the top cap layer serve as storage nodes for hole gas. The presence or absence of 2DHG results in two levels of drain current which are taken as logic '0' or '1'. Our studies reveal that this structure may work as a capacitorless DRAM.

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“…The significant advantage over the conventional DRAM design is the absence of the charge-storage capacitor (1T-DRAM), that makes compatible the co-integration with other CMOS circuit elements, resulting in cost effective manufacturing. Although quite a few contenders have been reported for capacitorless DRAM design, three solutions can be highlighted: the A2RAM [2], the MSDRAM [3] and the Z 2 -FET [4], which have their own pros and cons. The main benefits of favoring the Z 2 -FET over the others are performance, CMOS compatible fabrication and possibility of using ultra-thin bodies (UTB) without suffering from the supercoupling effect [6].…”

mentioning

confidence: 99%

“…In order to operate the device as a memory, the gate terminals are biased with V F G > 0 V and V BG < 0 V to induce a complementary energy barrier, i.e. a P-N junction, at the boundary between the gated and ungated sections of the body [4], [5]. As a result, the device ends up as a N + -P-N-P + structure emulating a Shockley diode [7] with three homo-junctions (J1-3), Fig.…”

mentioning

confidence: 99%

“…1b) are forward biased, the barriers collapse and the conductance hugely increases; this is the '1'-state. On the other hand, if the carrier concentration is reduced, energy barriers grow as in the deep depletion regime for a MOS capacitor [8], and the injection when reading is not enough to reduce the barriers [4], [5]. The conductivity then remains low, '0'-state, Fig.…”

mentioning

confidence: 99%

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${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

Navarro

Duan

Parihar

et al. 2017

IEEE Trans. Electron Devices

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Abstract-2D numerical simulations are used to demonstrate the Z 2 -FET as a competitive embedded capacitor-less DRAM cell for low-power applications. Experimental results in 28 nm FD-SOI technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.

show abstract

A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration

Cited by 113 publications

References 10 publications

Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Simulation of Capacitorless Memory Cell Based on GaN/AlGaN/GaN heterostructures

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

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