A compact design of SEED block cipher

Pirpilidis, Filippos; Kitsos, Paris; Kakarountas, Athanasios

doi:10.1109/meco.2015.7181881

Cited by 3 publications

(3 citation statements)

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“…So, reliable comparisons in term of the covered area between the proposed architecture and the other previously published architectures are impossible. Table 4 gives comparisons with previously published architectures for SEED cipher [7,8], [20,21] and for Present cipher [22][23][24]. Present is part of the ISO/IEC 29192-2:2012 standard [25] that specifies lightweight block ciphers suitable for IoT.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

“…Present is part of the ISO/IEC 29192-2:2012 standard [25] that specifies lightweight block ciphers suitable for IoT. In [7], a compact 16-datapath architecture is proposed. The implementation requires 2438 LUTs and produces the output after 479 clock cycles and achieves a data throughput of 29.7 Mbps at 111 MHz clock frequency.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

“…Although there are several compact implementations of AES and some for Camellia, there are not many efficient compact implementations of SEED. An example is paper [7], which presents a compact implementation of SEED that supports 16‐bit data input/output and 16‐bit internal data path. Also, in [8] an SEED implementation is proposed that supports 32‐bit data input/output but uses a 64‐bit internal data path.…”

Section: Introductionmentioning

confidence: 99%

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8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis

Pyrgas

Kitsos

2020

IET Circuits, Devices & Systems

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This study presents an 8-bit serialised architecture of SEED block cipher for constrained devices. The circuit utilises 356 FPGA slices and 447 1-bit registers flip-flops (FFs) in the BASYS3 board, operates with an 8-bit datapath and is aimed for use on area constraints devices. In order to keep the usage of hardware resources to a minimum but, at the same time, achieve a high level of security, the key generation process of SEED is implemented through an on-the-fly procedure. In addition, the necessary S-boxes are implemented using composite field arithmetic without using any block RAMs, resulting in a very compact implementation. The proposed architecture achieves a maximum frequency equal to 125 MHz with a total latency of 280 clock cycles and a throughput up to 57.1 Mbps for encryption or decryption.

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