A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM

Abstract

Abstract:In digital pixel sensors (DPS), memory elements typically occupy large silicon area of the pixel, which significantly reduces the pixel's fill factor while increases its size, power and cost. In this work, we propose to reduce DPS memory's area and power overhead by reducing the memory requirements with a multi-reset integration scheme, and meanwhile employing a dynamic memory instead of traditionally exploited large 6T-SRAM cell. The operation of the DPS takes advantage from the chronological change of the code, which results in reduced memory needs without affecting the light resolution. In the proposed implementation, a 4-bit in-pixel memory is used to reduce the pixel size, and an 8-bit resolution is achieved with multi-reset scheme. In addition, full complementary metal-oxide-semiconductor (CMOS) 2T DRAM and selective refresh scheme are adopted to implement the memory elements and further increase the area savings. This paper presents the proposed multi-reset integration methodology and its implementation with dedicated memory circuits. Proposed architecture is validated by a prototype chip fabricated using AMS 0.35 µm CMOS technology. Reported experimental results are compared with relative works.

A Review of Optical Sensors in CMOS

“…Figure 11c depicts the general structure of a digital pixel sensor (DPS), where the data conversion from the analog to the digital domain is carried out at the pixel level by a dedicated ADC controlled by the reset and select signals [65,[99][100][101][102][103]. The output of each pixel is a digital signal with all ADCs working in parallel.…”