2022
DOI: 10.1109/tpel.2021.3092367
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A Compact Double-Sided Cooling 650V/30A GaN Power Module With Low Parasitic Parameters

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Cited by 43 publications
(4 citation statements)
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“…and the package in which the die is placed is designed and implemented. This method has also reported results of less than 1 nH parasitic inductance in experimental results [20], [21], [22].…”
Section: Ferrite Beadsmentioning
confidence: 67%
See 1 more Smart Citation
“…and the package in which the die is placed is designed and implemented. This method has also reported results of less than 1 nH parasitic inductance in experimental results [20], [21], [22].…”
Section: Ferrite Beadsmentioning
confidence: 67%
“…And lastly is the approach to optimise the device packaging. In this approach, only the die of the switching device is used, [15], [16], [13], [17], [18], [19], [20], [21], [22] Slower switching  A resistor on the gate terminal or slower slew rate of the gate driver  straightforward to implement  Not very effective in reducing oscillations  Increase in switching losses [23], [24].…”
Section: B Minimisation Of Parasitic Inductancementioning
confidence: 99%
“…Therefore, by using the aforementioned techniques it is possible to achieve the structures shown in figures 6(a)-9(a). For a top and bottom heat sink configuration Li et al demonstrated the implementation of a doublesided cooling solution for GaN HEMTs which can be used to produce the heat sink configurations illustrated in figures 8(a) and 9(a) [45]. Even though there are several growth and processing challenges, such as avoiding surface damage on the top of the device, wafer bow and high residual thermal stress [46], ensuring a voidless GaN/diamond interface [47] and interface robustness [48], among other challenges, these problems are not insurmountable and the thermal management of future generations of AlGaN/GaN HEMT devices can be enhanced.…”
Section: Resultsmentioning
confidence: 99%
“…For a significant improvement of the thermal path from the junction to the heat sink, a double‐sided cooling approach is presented in ref. [19]. The GaN bare dies are soldered to a direct plated copper (DPC) substrate on both their top‐ and bottom‐sides.…”
Section: State Of Researchmentioning
confidence: 99%