A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

Piro, F.; Rinella, G. Aglieri; Andronic, A.; Antonelli, M.; Aresti, M.; Baccomi, Roberto; Becht, Pascal; Beolè, S.; Braach, Justus; Buckland, Matthew Daniel; Buschmann, E.; Camerini, P.; Carnesecchi, F.; Cecconi, Leonardo; Charbon, Edoardo; Contin, G.; Dannheim, D.; Melo, J. De; Deng, W.; Mauro, A. Di; Vassilev, Mirella Dimitrova; Emiliani, S.; Hasenbichler, Jan Anton; Hillemanns, H.; Hong, Geun Hee; Isakov, Artem; Junique, Antoine Jean-Simon; Kotliarov, Artem; Kugathasan, T.; L., Lautner,; Lemoine, Christophe; Mager, M.; Marras, D.; Martinengo, P.; Masciocchi, S.; Menzel, Marius; Münker, Magdalena; Rashevskaya, I.; Rebane, K.; Reidt, F.; Russo, Roberto; Sanna, I.; Sarritzu, Valerio; Senyukov, S.; Snoeys, W.; Sonneveld, J.; Šuljić, M.; Švihra, Peter; Tiltmann, N.; Usai, G. L.; Beelen, J. B. Van; Vernieri, C.; Villani, A.

doi:10.1109/tns.2023.3299333

Cited by 7 publications

(5 citation statements)

References 17 publications

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“…The DPTS features a 32 × 32 pixel matrix with a pitch of 15 µm implemented in the modified-with-gap process and contains a full digital front-end with asynchronous readout [7]. The sensor is controlled by a set of external reference currents and voltages and read out via a current mode logic (CML) output [8,9]. All the pixels are read out simultaneously via a differential digital output that time encodes the pixel position and Time-over-Threshold (ToT).…”

Section: Digital Pixel Test Structurementioning

confidence: 99%

First measurements with monolithic active pixel test structures produced in a 65 nm CMOS process

Buckland

2024

J. Inst.

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The Inner Tracking System (ITS) of the ALICE experiment at CERN will undergo an upgrade during the LHC long shutdown 3, in which the three innermost tracking layers will be replaced. This upgrade, named the Inner Tracking System 3 (ITS3), employs stitched wafer-scale Monolithic Active Pixel Sensors fabricated in a 65 nm CMOS process. The sensors are 260 mm in length and thinned to less than 50 μm then bent to form truly half-cylindrical half-barrels. The feasibility of this process for the ITS3 was explored with the first test production run (MLR1) in 2021, whose goal was to evaluate the charged particle detection efficiency and the sensor performance under non-ionising and ionising radiation up to the expected levels for ALICE ITS3 of 1013 1 MeV neq cm-2 (NIEL) and 10 kGy (TID). Three sensor flavours were produced to investigate this process: Analog Pixel Test Structure (APTS), Circuit Exploratoire 65 (CE65) and Digital Pixel Test Structure (DPTS). This contribution gives an overview of the MLR1 submission and test results, describing the different sensor flavours and presenting the results of the performance measurements done with particle beams for various chip variants and irradiation levels.

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Section: Digital Pixel Test Structurementioning

confidence: 99%

First measurements with monolithic active pixel test structures produced in a 65 nm CMOS process

Buckland

2024

J. Inst.

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“…A relevant study carried out on the DPTS chip is related to the chip performance at different power consumption regimes. Figure 5 shows the DPTS detection efficiency with different 𝐼 bias currents and, as a consequence, with a different power consumption, being the 𝐼 bias current the main biasing current of the front-end [7]. Except for the 𝐼 bias = 10 nA case, the efficiency reaches 99% or more for all the 𝐼 bias values and the power consumption estimation remains better than the target for the ALICE ITS3 (power consumption ∼15 mW cm −2 with 𝐼 bias = 30 nA).…”

Section: In-beam Measurementsmentioning

confidence: 99%

Validation of the 65 nm TPSCo CMOS imaging technology for the ALICE ITS3

Ferrero

2024

J. Inst.

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During the next Long Shutdown (LS3) of the LHC, planned for 2026, the innermost three layers of the ALICE Inner Tracking System will be replaced by a new vertex detector composed of curved ultra-thin monolithic silicon sensors. The R&D initiative on monolithic sensors of the CERN Experimental Physics Department, in cooperation with the ALICE ITS3 upgrade project, prepared the first submission of chip designs in the TPSCo 65 nm technology, called MLR1 (Multi Layer Reticle). It contains four different test structures with different process splits and pixel designs. These proceedings illustrate the first validation of the technology in terms of pixel performance and radiation hardness.

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“…The activation function available in the IPcore preprocessor was a slightly modified sigmoidal function. The function implemented in the SFSM module can be approximated by Equation (3).…”

Section: Neural Networkmentioning

confidence: 99%

“…However, a special place among these devices belongs to applicationspecific integrated circuits (ASICs). There are many examples presenting acceleration with dedicated integrated circuits in relation to convolutional neural networks [2], imaging technologies [3], cryptography in soft processors [4] or biomedical signal processing [5]. In this work, the authors focus mainly on biomedical data processing and medical applications.…”

Section: Introductionmentioning

confidence: 99%

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Baryczkowski,

Szczepaniak,

Matykiewicz

et al. 2023

Electronics

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The growing popularity of edge computing goes hand in hand with the widespread use of systems based on artificial intelligence. There are many different technologies used to accelerate AI algorithms in end devices. One of the more efficient is CMOS technology thanks to the ability to control the physical parameters of the device. This article discusses the complexity of the semiconductor implementation of TinyML edge systems in relation to various criteria. In particular, the influence of the model parameters on the complexity of the system is analyzed. As a use case, a CMOS preprocessor device dedicated to detecting heart rate in wearable devices is used. The authors use the current and weak inversion operating modes, which allow the preprocessor to be powered by cells of the human energy harvesting class. This work analyzes the influence of tuning hyperparameters of the learning process on the performance of the final device. This article analyzes the relationships between the model parameters (accuracy and neural network size), input data parameters (sampling rates) and CMOS circuit parameters (circuit area, operating frequency and power consumption). Comparative analyses are performed using TSMC 65 nm CMOS technology. The results presented in this article may be useful to direct this work with the model in terms of the final implementation as the integrated circuit. The dependencies summarized in this work can also be used to initially estimate the costs of the hardware implementation of the model.

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A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology

Cited by 7 publications

References 17 publications

First measurements with monolithic active pixel test structures produced in a 65 nm CMOS process

First measurements with monolithic active pixel test structures produced in a 65 nm CMOS process

Validation of the 65 nm TPSCo CMOS imaging technology for the ALICE ITS3

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

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