A compact spike-timing-dependent-plasticity circuit for floating gate weight implementation

Smith, Andy; McDaid, Liam; Hall, Steve

doi:10.1016/j.neucom.2013.07.007

Cited by 10 publications

(9 citation statements)

References 40 publications

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“…In the case of a volatile memory, such as static random-access memory (SRAM), high standby power consumption will be an issue. Therefore, some researchers have studied floating-gate-based synaptic devices with the spike-timing-dependent plasticity (STDP) of biological synapses [5], [6], as shown in Fig. 1 Floating-gate memory can reproduce the STDP of a biological synapse by exploiting the amount of injected charges.…”

Section: Generation Of Stdp With Non-volatile Tunnel-fet Memory For Lmentioning

confidence: 99%

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Kino

Fukushima

Tanaka

2020

IEEE J. Electron Devices Soc.

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Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This paper reports the I-V, programing, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.

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Section: Generation Of Stdp With Non-volatile Tunnel-fet Memory For Lmentioning

confidence: 99%

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Kino

Fukushima

Tanaka

2020

IEEE J. Electron Devices Soc.

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“…The quantity of charge stored on the SiN spacer represents the weight value in neural network implementations. In this way, the charge stored on the SiN spacer in the NOI device provides electronically adjustable and non-volatile scale factors for the output currents [8,10].…”

Section: Noi Synaptic Modelmentioning

confidence: 99%

“…In addition, the advantages of hardware realizations include high computation speed and relative ease of integration with analog interface. There are many varieties of structures and computational methods containing digital and analog forms in hardware neural implementation in past studies [7][8][9][10][11][12][13][14]. Among different concepts, the NVM device is considered the most promising for its analog memory nature and small chip area.…”

Section: Introductionmentioning

confidence: 99%

Non-overlapped implantation (NOI) MOSFET synapse and its implementation on supervised neural network

et al. 2015

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“…Moreover, this architecture is designed for the simulation of simple and specific SNN models that do not take plasticity of synapses into consideration. This has special relevance since plasticity [16][17][18] is an important feature to be taken into account while considering real-time self-evolving neu-romorphic systems, which is the target of simulators [14,[19][20][21]. Apart from this architecture, Zamarreño et al [13] proposed a scalable-reconfigurable neuromorphic Address Event Representation (AER) configured as 2D mesh.…”

Section: Introductionmentioning

confidence: 99%

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

et al. 2018

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Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities.

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A compact spike-timing-dependent-plasticity circuit for floating gate weight implementation

Cited by 10 publications

References 40 publications

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Non-overlapped implantation (NOI) MOSFET synapse and its implementation on supervised neural network

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

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