A comparative investigation of low work‐function metal implantation in the oxide region for improving electrostatic characteristics of charge plasma TFET

Aslam, Mohd.; Sharma, Dheeraj; Yadav, Shivendra; Soni, Deepak; Sharma, Neeraj; Gedam, Anju

doi:10.1049/mnl.2018.5390

Cited by 12 publications

(6 citation statements)

References 27 publications

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“…RDF was found to cause a significant variance in the threshold voltage (V T ) and SS between devices [37,38]. Thus, to address this issue, dopingless TFETs (DL-TFETs) are rapidly becoming reliable candidates based on the charge plasma concept necessary for the formation of source and drain regions [39][40][41][42][43][44]. To date, charge plasma-based DL-TFETs have played a crucial role in solving the RDF issue frequently occurring in sub-5 nm technology nodes.…”

Section: Introductionmentioning

confidence: 99%

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Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor

Kim¹,

Kim²,

Kim³

et al. 2022

Nanotechnology

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Tunnel field-effect transistors (TFETs) have garnered great interest as an option for the replacement of metal–oxide–semiconductor field-effect transistors owing to their extremely low off-current and fast switching suitable for low-power-consumption applications. However, conventional doped TFETs have the disadvantage of introducing undesirable random dopant fluctuation (RDF) events, which cause a large variance in the threshold voltage and ambipolar leakage current at negative gate voltages. In this study, a simple approach for charge plasma-based doping-less tunnel field-effect transistors (DL-TFETs), including the Ge/Si bilayer frame, which affects the RDF and low on-current issues, was developed by the commercially available Silvaco Atlas device simulator. The use of the Ge/Si bilayer enhances the on-current and point subthreshold swing to 1.4 × 10−6 A and 16.6 mV/dec, respectively. In addition, the dependencies of the Ge/Si junction boundary position and Ge content were examined systematically to attain a firm understanding of the electrical features in DL-TFETs.

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Section: Introductionmentioning

confidence: 99%

“…Thus, numerous studies have been dedicated to solving the aforementioned issues in DL-TFET devices. One example is the insertion of a metal splint between the gate electrode and source or drain electrode to enhance the oncurrent [44]. The other is bandgap engineering by controlling the material or thickness of the body [45].…”

Section: Introductionmentioning

confidence: 99%

Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor

Kim¹,

Kim²,

Kim³

et al. 2022

Nanotechnology

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show abstract

“…Although the new structures can solve the problem to a certain extent, the device performance still has room for improvement. The size scale application of TFETs is limited by the lower on-current, larger miller capacitance, and the heavily doped steep junctions [17,18]. Therefore, it is necessary to further study the new structure and technology of TFET.…”

Section: Introductionmentioning

confidence: 99%

TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

et al. 2020

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The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

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“…As a whole, TFETs reported in recent years adopt abrupt junction at tunneling interface, which leads to a complex fabrication processes and a high thermal budget. In addition, a heavily doped concentration in the channel and active region are also challenging during the fabrication process and it is easy to be influenced by random dopant fluctuations (RDFs) [17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

et al. 2019

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This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

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A comparative investigation of low work‐function metal implantation in the oxide region for improving electrostatic characteristics of charge plasma TFET

Cited by 12 publications

References 27 publications

Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor

Simple Ge/Si bilayer junction-based doping-less tunnel field-effect transistor

TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

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