A comparative study of modelling at different levels of abstraction in system on chip designs: a case study

Jayadevappa, Suryaprasad; Shankar, Ravi; Mahgoub, Imad

doi:10.1109/isvlsi.2004.1339508

Cited by 8 publications

(2 citation statements)

References 15 publications

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“…These include SystemVerilog [Rich 2004], SystemC [Grötker et al 2002, SpecC [Fujita and Ra 2001], and Handel-C [Loo et al 2002], among others [Habibi and Tahar 2003]. Such system description languages (SDLs) can characterize designs at a variety of levels of abstraction, enabling extremely compact system descriptions early in the design flow and fast simulation without compromising accuracy [Jayadevappa et al 2004]. In particular, SystemC, a C++-based library that provides a variety of hardware-oriented constructs and an event-based simulation kernel, has gained wide acceptance, especially as a tool for early design space exploration.…”

Section: Related Workmentioning

confidence: 99%

Accurate and fast system-level power modeling

Varma

Jacob

Debes

et al. 2007

ACM Trans. Embed. Comput. Syst.

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Accurate and fast system modeling is central to the rapid design space exploration needed for embedded-system design. With fast, complex SoCs playing a central role in such systems, system designers have come to require MIPS-range simulation speeds and near-cycle accuracy. The sophisticated simulation frameworks that have been developed for high-speed system performance modeling do not address power consumption, although it is a key design constraint. In this paper, we define a simulation-based methodology for extending system performance-modeling frameworks to also include power modeling. We demonstrate the use of this methodology with a case study of a real, complex embedded system, comprising the Intel XScale ® embedded microprocessor, its WMMX TM SIMD coprocessor, L1 caches, SDRAM and the on-board address and data buses. We describe detailed power models for each of these components and validate them against physical measurements from hardware, demonstrating that such frameworks enable designers to model both power and performance at high speeds without sacrificing accuracy. Our results indicate that the power estimates obtained are accurate within 5% of physical measurements from hardware, while simulation speeds consistently exceed a million instructions per second (MIPS).Article 26 / 2 • A. Varma et al.

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Section: Related Workmentioning

confidence: 99%

Accurate and fast system-level power modeling

Varma

Jacob

Debes

et al. 2007

ACM Trans. Embed. Comput. Syst.

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“…In SoC design flow, checking concepts with SystemC allows higher level of simulation than gate level one provided by HDL simulators. It enables to reduce times of simulation [2], with an acceptable accuracy [3]. Furthermore, this tool can be used as an efficient simulator for analog or mixed signals systems [4], [5].…”

Section: Introductionmentioning

confidence: 99%

SystemC validation of a low power analog CMOS image sensor architecture

Verdant

Villard

Dupret³

et al. 2007

2007 IEEE Northeast Workshop on Circuits and Systems

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In a context of embedded steady camera for video surveillance with high performance requirements and hard power consumption constraints, a low power CMOS image sensor architecture allowing sensor's acuity adaptation to the scene activity is considered. In this paper we present an original approach based on SystemC modeling to validate a complex analog SIMD architecture (i.e. highly parallel and programmable) and the implemented algorithm.

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