A comparative study of power efficient SRAM designs

Hezavei, J.; Narayanan, Vijaykrishnan; Irwin, M.J.

doi:10.1145/330855.331018

Cited by 9 publications

(5 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Note that the background, pre-charge, and access power consumed in a DRAM should have no dependence on the data [22]. Note that this test is similar to one performed on SRAMs in [17].…”

Section: A Data Dependence Of Power Consumptionmentioning

confidence: 99%

“…To the best of our knowledge, [16] is the only study to present measured DIMM power variability; it explored running systems, including component-level sources such as CPUs and DDR2 DRAMs but primarily focused on vendor-dependent variations. The study in [17] included an investigation on operation and data dependence of memory power, but used SRAMs on an older 0.35 m process node.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Power Variability in Contemporary DRAMs

Gottscho

Kagalwalla

Gupta

2012

IEEE Embedded Syst. Lett.

View full text Add to dashboard Cite

Abstract-Technology scaling has led to significant variability in chip performance and power consumption. In this work, we measured and analyzed the power variability in dynamic random access memories (DRAMs). We tested 22 double date rate third generation (DDR3) dual inline memory modules (DIMMs), and found that power usage in DRAMs depends on both operation type (write, read, and idle) as well as data, with write operations consuming more than reads, and 1s in the data generally costing more power than 0s. Temperature had little effect (1-3%) across the 50 C to 50 C range. Variations were up to 12.29% and 16.40% for idle power within a single model and for different models from the same vendor, respectively. In the scope of all tested 1 gigabyte (GB) modules, deviations were up to 21.84% in write power. Our ongoing work addresses memory management methods to leverage such power variations.Index Terms-Double data rate third generation (DDR3), dynamic random access memory (DRAM), power, variability.

show abstract

“…Note that the background, pre-charge, and access power consumed in a DRAM should have no dependence on the data [22]. Note that this test is similar to one performed on SRAMs in [17].…”

Section: A Data Dependence Of Power Consumptionmentioning

confidence: 99%

mentioning

confidence: 99%

Power Variability in Contemporary DRAMs

Gottscho

Kagalwalla

Gupta

2012

IEEE Embedded Syst. Lett.

View full text Add to dashboard Cite

show abstract

“…Su and Despain [1995] investigate vertical and horizontal cache partitioning, as well as Gray code addressing to reduce dynamic power. Hezavei et al [2000] study the effectiveness of different low power SRAM design strategies such as divided bitline, pulsed wordline, and isolated bitline. Energy savings can also be achieved by dynamically [Balasubramonian et al 2000;Dropsho et al 2002] or statically [Albonesi 1999;Zhang et al 2002Zhang et al , 2003 reconfiguring cache characteristics such as cache size, cache associativity, and cache active ways.…”

Section: Low-level Techniquesmentioning

confidence: 99%

IATAC: a smart predictor to turn-off L2 cache lines

Abella

González²,

Vera³

et al. 2005

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

As technology evolves, power dissipation increases and cooling systems become more complex and expensive. There are two main sources of power dissipation in a processor: dynamic power and leakage. Dynamic power has been the most significant factor, but leakage will become increasingly significant in future. It is predicted that leakage will shortly be the most significant cost as it grows at about a 5× rate per generation. Thus, reducing leakage is essential for future processor design. Since large caches occupy most of the area, they are one of the leakiest structures in the chip and hence, a main source of energy consumption for future processors.This paper introduces IATAC (inter-access time per access count), a new hardware technique to reduce cache leakage for L2 caches. IATAC dynamically adapts the cache size to the program requirements turning off cache lines whose content is not likely to be reused. Our evaluation shows that this approach outperforms all previous state-of-the-art techniques. IATAC turns off 65% of the cache lines across different L2 cache configurations with a very small performance degradation of around 2%.

show abstract

“…Hezavei et al [39] propose techniques such as divided bitline, pulsed wordline and isolated wordline to reduce cache energy consumption. Kuroda et al [55] propose a scheme based on Vcc and threshold voltage scaling for low power high-speed CMOS digital design.…”

Section: High-level Techniquesmentioning

confidence: 99%

Cache designs for reliable hybrid high and ultra-low voltage operation

Maric

View full text Add to dashboard Cite

Increasing demand for implementing highly-miniaturized battery-powered ultra-low-cost systems (e.g., below 1 USD) in emerging applications such as body, urban life and environment monitoring, etc., has introduced many challenges in the chip design. Such applications require high performance occasionally, but very little energy consumption during most of the time in order to extend battery lifetime. In addition, they require real-time guarantees. The most suitable technological solution for those devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/sub-threshold (NST) voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and it is mandatory trading off different SRAM designs, especially in cache memories, which occupy most of the processor¿s area. In this Thesis, we analyze the performance/power tradeoffs involved in the design of SRAM L1 caches for reliable hybrid high and NST Vcc operation from a microarchitectural perspective. We develop new, simple, single-Vcc domain hybrid cache architectures and data management mechanisms that satisfy all stringent needs of our target market. Proposed solutions are shown to have high energy efficiency with negligible impact on average performance while maintaining strong performance guarantees as required for our target market.

show abstract

A comparative study of power efficient SRAM designs

Abstract: ABSTRACT

Cited by 9 publications

References 9 publications

Power Variability in Contemporary DRAMs

Power Variability in Contemporary DRAMs

IATAC: a smart predictor to turn-off L2 cache lines

Cache designs for reliable hybrid high and ultra-low voltage operation

Contact Info

Product

Resources

About