with ever growing technology scaling, low power operation has become a necessity in VLSI design. Sigma Delta ADC consists major portions of the modern VLSI designs, thus efforts are being made to design low power ,small area sigma delta ADCs using different topologies and methodologies. This paper discusses various existing Sigma Delta modulator designs and topologies, consisting of different number stages and optimizations from one another. This paper focuses on the study of these designs and their comparison on the basis of parameters like power dissipation, structure order, bandwidth, OSR, FOM etc. All the designs studies are application and technology specific but the output bit patterns are similar for similar inputs with variations in rate of output. The simulation environment for the structures was chosen to be PSPICE A/D 16.6 and Sigma Delta Toolbox of MATLAB R2014a. Keywords: Sigma Delta ADC, Oversampling, SNR, SNDR, FOM, PSPICE.
I.INTRODUCTION Sigma Delta modulators (DSMs) are a class of oversampling analog-to-digital converters (ADCs) that perform "quantization noise shaping," thus achieving a high signal-to-noise ratio (SNR). An efficient solution for resolutions above approximately 12 bits, DSMs are extensively used in analog and RF applications. In this article, we study the fundamentals of this vast field. Sigma-delta (SD) analog-to-digital converters (ADCs) are employed over a wide range of applications, from low frequency instrumentation to high-speed communication circuits .Continuous-time sigma-delta modulators (CT-SDMs) provide meaningful advantage over their discrete-time (DT) counterparts, as such as lower power consumption, wider input signal bandwidth and implicit anti-alias filter (AAF). Thus, they have been a good choice for power-efficient, high and medium to high resolution SD ADCs targeted to wireless wideband high-speed applications in advanced CMOS technologies. Based on this properties many CTSDM with signal bandwidth of 0.5 MHz to 20 MHz are reported in the literature. Discrete-time (DT), switched-capacitor circuits are a widespread tool for implementing SD data converters. These data converters are pushed by an increasing demand for higher rates and lower consumption SD converters in order to handle, e.g. current mobile high bandwidth communication systems. DT Modulators have enhanced their performance due to the improvement in microelectronics manufacturing methods along with architectures that work accurately in the discrete domain. Sigma-delta converters operation is based on the quantization noise shaping principle. The signal processing path is built in such a way that noise spectrum transformation is different from signal spectrum transformation. In this case signal transformation is characterized by signal transfer function (STF) while noise transformation is characterized by noise transfer function (NTF).[1] The evolution of the CMOS technology during the last decades has allowed the presence of electronic systems in many aspects of our daily life: automotive, ...