A Comparison of Compiler Tiling Algorithms

Rivera, Gabriel; Tseng, Chau‐Wen

doi:10.1007/978-3-540-49051-7_12

Cited by 45 publications

(73 citation statements)

References 30 publications

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“…After extensive experimentation we found that Chame and Moon's algorithm tends to perform consistently better than other heuristics [3,4,12] when the tile size is reduced to cope with cache sharing. We note however that it is beyond the scope of this paper to investigate thoroughly the relative performance of tiling algorithms on SMT processors.…”

Section: Dynamic Tiling Copying and Block Data Layoutmentioning

confidence: 95%

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Code and Data Transformations for Improving Shared Cache Performance on SMT Processors

Nikolopoulos

2003

Lecture Notes in Computer Science

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Abstract. Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessive conflict misses. This paper proposes software solutions for dynamically partitioning the shared cache of an SMT processor, via the use of three methods originating in the optimizing compilers literature: dynamic tiling, copying and block data layouts. The paper presents an algorithm that combines these transformations and two runtime mechanisms to detect cache sharing between threads and react to it at runtime. The first mechanism uses minimal kernel extensions and the second mechanism uses information collected from the processor hardware counters. Our experimental results show that for regular, perfect loop nests, these transformations are very effective in coping with shared caches. When the caches are shared between threads from the same address space, performance is improved by 16-29% on average. Similar improvements are observed when the caches are shared between threads from different address spaces. To our knowledge, this is the first work to present an all-software approach for managing shared caches on SMT processors. It is also one of the first performance and program optimization studies conducted on a commercial SMT-based multiprocessor using Intel's hyperthreading technology.

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Section: Dynamic Tiling Copying and Block Data Layoutmentioning

confidence: 95%

“…It is used extensively in scientific libraries such as LAPACK. It is also the target of numerous compiler optimizations for memory hierarchies [3,4,6,9,12,17].…”

Section: Introductionmentioning

confidence: 99%

Code and Data Transformations for Improving Shared Cache Performance on SMT Processors

Nikolopoulos

2003

Lecture Notes in Computer Science

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“…Conflict misses [20] may occur when too many data items map to the same set of cache locations, causing cache lines to be flushed from cache before they may be used, despite sufficient capacity in the overall cache. As a result, in addition to eliminating capacity misses [11], [23] and maximizing cache utilization, the tile should be selected in such a way that there are no (or few) self conflict misses, while cross conflict misses are minimized [3], [4], [5], [10], [17].…”

Section: Related Workmentioning

confidence: 99%

“…Unfortunately, the performance of a tiled program resulting from existing tiling heuristics does not have robust performance [13], [17]. Instability comes from the so-called pathological array sizes, when array dimensions are near powers of two, since cache interference is a particular risk at that point.…”

Section: Related Workmentioning

confidence: 99%

“…It introduces space overhead but effectively stabilizes program performance. Cache utilization for padded benchmark codes is much higher overall, since padding is used to avoid small tiles [17]. As a result, more recent research efforts have investigated the combination of both loop tiling and array padding in the hope that both magnitude and stability of performance improvements of tiled programs can be achieved at the same time.…”

Section: Related Workmentioning

confidence: 99%

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Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures

Athanasaki

Kourtis

Anastopoulos

et al. 2005

Advances in Informatics

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Abstract. Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program transformations, have been shown to be an effective approach to improving locality and cache exploitation, especially for dense matrix scientific computations. Beyond loop nest optimizations, data transformation techniques, and in particular blocked data layouts, have been used to boost the cache performance. The stability of performance improvements achieved are heavily dependent on the appropriate selection of tile sizes.In this paper, we investigate the memory performance of blocked data layouts, and provide a theoretical analysis for the multiple levels of memory hierarchy, when they are organized in a set associative fashion. According to this analysis, the optimal tile size that maximizes L1 cache utilization, should completely fit in the L1 cache, even for loop bodies that access more than just one array. Increased self-or/and cross-interference misses can be tolerated through prefetching. Such larger tiles also reduce mispredicted branches and, as a result, the lost CPU cycles that arise. Results are validated through actual benchmarks on an SMT platform.

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Efficient search‐space pruning for integrated fusion and tiling transformations

Gao¹,

Krishnamoorthy²,

Sahoo³

et al. 2007

Concurrency and Computation

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Compile‐time optimizations involve a number of transformations such as loop permutation, fusion, tiling, array contraction etc. The selection of the appropriate transformation to minimize the execution time is a challenging task. We address this problem in the context of tensor contraction expressions involving arrays too large to fit in main memory. Domain‐specific features of the computation are exploited to develop an integrated framework that facilitates the exploration of the entire search space of optimizations. In this paper, we discuss the exploration of the space of loop fusion and tiling transformations in order to minimize the disk I/O cost. These two transformations are integrated and pruning strategies are presented that significantly reduce the number of loop structures to be evaluated for subsequent transformations. The evaluation of the framework using representative contraction expressions from quantum chemistry shows a dramatic reduction in the size of the search space using the strategies presented. Copyright © 2007 John Wiley & Sons, Ltd.

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A Comparison of Compiler Tiling Algorithms

Cited by 45 publications

References 30 publications

Code and Data Transformations for Improving Shared Cache Performance on SMT Processors

Code and Data Transformations for Improving Shared Cache Performance on SMT Processors

Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures

Efficient search‐space pruning for integrated fusion and tiling transformations

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