A comparison of parallel multipliers with neuron MOS and CMOS technologies

Hirose, Kei; Yasuura, H.

doi:10.1109/apcas.1996.569320

Cited by 6 publications

(2 citation statements)

References 2 publications

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“…Comparison of the areas of multiple-input threshold logic circuits based on nMOS and CMOS structures made in Ref. 11 shows that the layout area in the nMOS structures is 5060% smaller.…”

Section: Structure Of the Thinning/shrinking Cellular Automaton Circuitmentioning

confidence: 99%

?MOS cellular-automaton circuit for picture thinning and shrinking

Ikebe¹,

Kameishi²,

Amemiya³

1999

Elect. Eng. Jpn.

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In this study we propose a design for an LSI circuit that implements a cellular automaton. The cellular automaton is a parallel and distributed architecture device suitable for high‐speed image processing. To develop a cellular automaton LSI circuit, it is necessary to design small‐size unit cell circuits that can operate according to cell–cell interaction rules. We propose to use νMOSFET devices for such cell circuits. Template matching is implemented by combining multiple input νMOSFET circuits and inverters. A cell circuit was designed for image thinning and shrinking, and its operation was analyzed using a circuit simulator. It was demonstrated that high speed operation (up to 100 MHz clock frequency) can be obtained. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 41–48, 1999

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“…Comparison of the areas of multiple-input threshold logic circuits based on nMOS and CMOS structures made in Ref. 11 shows that the layout area in the nMOS structures is 5060% smaller.…”

Section: Structure Of the Thinning/shrinking Cellular Automaton Circuitmentioning

confidence: 99%

?MOS cellular-automaton circuit for picture thinning and shrinking

Ikebe¹,

Kameishi²,

Amemiya³

1999

Elect. Eng. Jpn.

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“…The use of neu-MOS transistors provides additional functionality which allows, for example, the design of a full adder cell with only eight transistors as compared to 28 in CMOS and an area of 55% of the CMOS design [2].…”

Section: Introductionmentioning

confidence: 99%

Novel extension of neu-MOS techniques to neu-GaAs

Celinski

Abbott

Al-Sarawi

et al. 2000

Microelectronics Journal

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The neuron-MOS (neu-MOS) transistor, recently discovered by Shibata and Ohmi in 1991 [T. Shibata, T. Ohmi, International Electron Devices Meeting, Technical Digest, 1991] uses capacitively coupled inputs onto a floating gate. Neu-MOS enables the design of conventional analog and digital integrated circuits with a significant reduction in transistor count [L. This paper extends the neu-MOS paradigm to complementary gallium arsenide based on HIGFET transistors. The design and HSPICE simulation results of a neu-GaAs ripple carry adder are presented, demonstrating the potential for very significant transistor count and area reduction through the use of neu-GaAs in VLSI design. Preliminary simulations indicate a reduction of a factor of four in transistor count for the same power dissipation as conventional complementary GaAs. The small gate leakage is shown to be useful in eliminating unwanted charge build-up on the floating gate.

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