A comparison of two SAR processing architectures for VLSI implementation

Abstract

Digital processing of Synthetic Aperture Radar (SAR) data requires very large amounts of computation.In this paper we consider the feasibility of a VLSI implementation of the azimuth compression part of a real-time SAR processor.The area/size requirements of such a processor are evaluated by means of a prototype design. Two processing architectures are compared in terms of their suitability for VLSI implementation.