A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

Husseini, J. El; Garros, X.; Cluzel, J.; Subirats, A.; Makosiej, Adam; Weber, O.; Thomas, Olivier; Huard, V.; Federspiel, X.; Reimbold, G.

doi:10.1109/ted.2014.2361954

Cited by 9 publications

(2 citation statements)

References 21 publications

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“…Predominantly, integrating a nitration procedure and high-k substantial into gate oxide decreases the leakage current, but it improves the effects of BTI in the procedure of NBTI on PMOS and NMOS devices (Dounavi et al , 2019). BTI and HCI are the leading deprivation devices for the application fields which are taken into account in the present situation (El Husseini et al , 2014). BTI and HCI may produce circuit miscarriages by prompting time-dependent deviations on BTI transistors.…”

Section: Introductionmentioning

confidence: 99%

High throughput SRAM design for improved computing in autonomous systems

Neeraj

Das

2021

IJIUS

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Purpose High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances. Design/methodology/approach Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed. Findings Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes. Originality/value The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

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Section: Introductionmentioning

confidence: 99%

High throughput SRAM design for improved computing in autonomous systems

Neeraj

Das

2021

IJIUS

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“…Moreover, the BOX layer reduces the parasitic capacitance between the source node and the drain node. This feature of the 28-nm FD-SOI enables the production of ultra-low-power SRAMs [4][5][6][7][8].…”

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confidence: 99%

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme

Mori

Nakagawa

Kitahara

et al. 2019

IEEE Trans. Circuits Syst. I

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This paper presents a low-energy 64-Kb 8-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is 0.291 × 1.457 µm 2 . The test chip exhibits 0.48-V operation at access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.

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