A component-based specification approach for embedded systems using FDTs

Proceedings of the Conference on Design, Automation and Test in Europe

Pravadelli

2008

Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Similar approaches are applied in hardware verification and testing too, especially at RTL or gate level, where mutants are generally referred as faults, and mutation analysis is performed by means of fault modeling and fault simulation. However, in modern embedded systems there is a close integration between HW and SW parts, and verification strategies should be applied early in the design flow. This requires the definition of new mutation analysis-based strategies that work at system level, where HW and SW functionalities are not partitioned yet. In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions. In particular, the main constructs provided by the SystemC TLM 2.0 library have been analyzed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.

Section: The Efsm Modelmentioning

confidence: 99%

A mutation model for the SystemC TLM 2.0 communication interfaces

Proceedings of the Conference on Design, Automation and Test in Europe

Pravadelli

2008

“…The EFSM model is widely used for modeling complex systems like reactive systems [Koo et al 1999], communication protocols [Katagiri et al 2000], buses [Zitouni et al 2006] and controllers driving data-path [Guerrouat and Richter 2006]. Definition 1.…”

Section: Efsm Generationmentioning

confidence: 99%

A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications

ACM Trans. Des. Autom. Electron. Syst.

Vinco

2015

With the advent of heterogeneous multiprocessor system-on-chips (MPSoCs), hardware/software partitioning is again on the rise both in research and in product development. In this new scenario, implementing intellectual-property (IP) blocks as SW applications rather than dedicated HW is an increasing trend to fully exploit the computation power provided by the MPSoC CPUs. On the other hand, whole libraries of IP blocks are available as RTL descriptions, most of them without a corresponding high-level SW implementation. In this context, this article presents a methodology to automatically generate SW applications in C++, by starting from existing RTL IPs implemented in hardware description language (HDL). The methodology exploits an abstraction algorithm to eliminate implementation details typical of HW descriptions (such as cycle-accurate functionality and data types) to guarantee relevant performance of the generated code. The experimental results show that, in many cases, the C++ code automatically generated in a few seconds with the proposed methodology is as efficient as the corresponding code manually implemented from scratch. . 2015. A methodology to recover RTL IP functionality for automatic generation of SW applications.

“…The EFSM model is widely used for modeling complex systems like reactive systems [30], communication protocols [31], buses [32] and controllers driving data-path [33]. EFSM has been adopted in this work to easily represent communication protocols based on transactions as well as mutations on TLM code, as explained in Section 4.…”

Section: The Efsm Modelmentioning

confidence: 99%

Testbench Qualification of SystemC TLM Protocols through Mutation Analysis

Guarnieri

et al. 2014

IEEE Trans. Comput.

Transaction-level modeling (TLM) has become the de-facto reference modeling style for system-level design and verification of embedded systems. It allows designers to implement high-level communication protocols for simulations up to faster than at register-transfer level (RTL). To guarantee interoperability between TLM IP suppliers and users, designers implement the TLM communication protocols by relying on a reference standard, such as the standard OSCI for SystemC TLM. Functional correctness of such protocols as well as their compliance to the reference TLM standard are usually verified through user-defined testbenches, whose high quality and completeness play a key role for an efficient TLM design and verification flow. This article presents a methodology to apply mutation analysis, a technique applied in literature for SW testing, for measuring the testbench quality in verifying TLM protocols. In particular, the methodology aims at (i) qualifying the testbenches by considering both the TLM protocol correctness and their compliance to a defined standard (i.e., OSCI TLM), (ii) optimizing the simulation time during mutation analysis by avoiding mutation redundancies, and (iii) driving the designers in the testbench improvement. Experimental results on benchmarks of different complexity and architectural characteristics are reported to analyze the methodology applicability.