A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs

Huynh-Bao, T.; Sakhare, Sushil; Yakimets, D.; Ryckaert, Julien; Thean, Aaron; Mercha, A.; Verkest, D.; Wambacq, Piet

doi:10.1109/ted.2015.2504729

Cited by 31 publications

(17 citation statements)

References 10 publications

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“…read AT (RAT), is an important metric, which depends on read cell current through the access and pull‐down transistors. Similarly, the write AT (WAT) during the write mode is measured between the time when WL reaches to 50% of VDD and node V2 reaches to switching threshold voltage of the other inverter [24, 25]. Saini and Choudhary [19] suggested that the relative change in on‐current ( I on ) and device capacitance ( C gg ) is the prime factor to investigate the delay of the circuit.…”

Section: T Sram Design and Analysismentioning

confidence: 99%

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

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This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I on /C gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I on /I off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.

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Section: T Sram Design and Analysismentioning

confidence: 99%

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

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“…The N-channel and P-channel of LFETs are composed of strained Si and Si 0.5 Ge 0.5 respectively. For vertical devices, the channel is in a <100> direction and has no strain 10 . In VFETs, the channel length is defined by the thickness of the high-k/metal-gate and not confined by the device footprint.…”

Section: Device Characteristics and Performance Benchmaringmentioning

confidence: 99%

“…The three typical configurations of SRAM bitcells that have been widely adopted by the industry are high density (HD), low voltage (LV) and high performance (HP) 10 . The HP bitcell is designed by a NW ratio of 1:2:2, which can be used to improve the writeability.…”

Section: Layout Optimizationsmentioning

confidence: 99%

“…The RSNM is defined as the length of a side of the largest square that can be fitted into the lobes of the butterfly curve 10 . The read failure criteria for the static noise margin is the condition where the RSNM is below the thermal noise.…”

Section: Electrical Benchmarking For Sramsmentioning

confidence: 99%

“…The required density scaling of SRAMs has forced an aggressive metal pitch (MP) and contacted gate pitch (CGP) and demanded self-aligned quadruple patterning (SAQP) with 193i lithography or multiple EUVL exposures to meet the required constraints. Meanwhile, the CMOS scaling has placed SRAMs into the regime where it is substantially hard to meet the performance, energy and density requirements 10 . SRAMs have been more prone to process variability and difficult to compromise read and write margins due to 2X shrinking at every technology nodes.…”

Section: Introductionmentioning

confidence: 99%

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Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

et al. 2016

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In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the desired features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

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