A comprehensive comparison between double patterning and double patterning with spacer on sub-50nm product implementation

Tseng, Ching-Te; Yang, Chin-Cheng; Yang, Elvis; Yang, T. H.; Chen, K. C.; Lu, Chih‐Yuan

doi:10.1117/12.769904

Cited by 2 publications

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“…It was recently employed to trim-away printing assist features (PrAF) introduced to enhance the resolution of conventional single patterning [14]. A second hardmask layer is necessary in case of positive LELE process, but this does not represent an extra requirement because many standard DPL implementations favor the use of a second hardmask [3,15]. Relaxed CD and overlay requirements of the trim exposure, which are demonstrated by the results of our implementation, make process control an easy task.…”

Section: A Manufacturing Processmentioning

confidence: 99%

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Ghaida

Torres

Gupta

2011

IEEE Trans. Semicond. Manufact.

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Abstract-1 We propose shift-trim double patterning lithography (ST-DPL), a cost-effective double patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double-patterning (ST-DPL as well as standard DPL). 2× pitch relaxation being associated with a considerable area overhead, 1.8× pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<0.3% cell-area overhead) and no more than 4.7% cellarea overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double-patterning: (1) cuts mask-cost to nearly half, (2) reduces overlay errors between the two patterns, (3) alleviates the bimodal line-width distribution problem in double patterning, and (4) slightly enhances the throughput of critical-layer scanners.

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Section: A Manufacturing Processmentioning

confidence: 99%

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Ghaida

Torres

Gupta

2011

IEEE Trans. Semicond. Manufact.

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“…A second hardmask layer is necessary in case of positive LELE process. However, this does not represent an extra requirement since many standard DPL implementations favors the use of a second hardmask [7,10]. Requirements on trim-exposure are easy.…”

Section: Manufacturing Processmentioning

confidence: 99%

Single-mask double-patterning lithography

2009

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This paper proposes shift-trim double patterning lithography (ST-DPL), a cost-effective method for achieving 2× pitchrelaxation with a single photomask (especially at polysilicon layer). The mask is re-used for the second exposure by applying a translational mask-shift. Extra printed features are then removed using a non-critical trim exposure. The viability of ST-DPL is demonstrated. The proposed method has many advantages with virtually no area overhead (< 0.3% standard-cell area): (1) cuts mask-cost to nearly half that of standard-DPL, (2) reduces overlay errors between the two patterns and can virtually eliminate it in some process implementations, (3) alleviates the bimodal problem in doublepatterning, and (4) enhances throughput of first-rate scanners. We implement a small 45nm standard-cell library and small benchmark designs with ST-DPL to illustrate its viability.

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A comprehensive comparison between double patterning and double patterning with spacer on sub-50nm product implementation

Cited by 2 publications

References 0 publications

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Single-mask double-patterning lithography

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