A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model

Dang, Khanh N.; Ahmed, Akram Ben; Tran, Xuan‐Tu; Okuyama, Yuichi; Abdallah, Abderazek Ben

doi:10.1109/tvlsi.2017.2736004

Cited by 9 publications

(12 citation statements)

References 48 publications

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“…By using adaptive routing, we can maintain the reliability of the system, even under a high number of defects. We would like to note that there are some vulnerable links inside the network such as the link between Network Interface and router where a failure on one of these link immediately corrupt the system reliability [49]. However, since we mostly consider the inter-layer links (using TSVs) in this work, the LAFT routing algorithm can efficiently work without considering the vulnerability of those links.…”

Section: Network-on-chip Architecturementioning

confidence: 99%

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

et al. 2020

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As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Networkon-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles). INDEX TERMS 3D-ICs, fault-tolerance, error correction code, through-silicon-via, product code, parity check, networks-on-chip, fault-detection.

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Section: Network-on-chip Architecturementioning

confidence: 99%

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

et al. 2020

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“…NoC [6][7][8][9] interconnection consists of a group of shared router nodes joined by shared channels or links, making this structure more efficient than buses. The connections between the routers and their attached processing elements (PEs) are constructed by network interfaces (NIs) [10]. The functionality of an NoC is defined by its topology, routing algorithm, flow control, and switching technique.…”

Section: Introductionmentioning

confidence: 99%

“…Fault tolerance techniques are achieved mainly by redundancy, which can be time redundancy, such as data retransmission with the selfsame component, information redundancy by adding code for error correction, or spatial redundancy achieved by redundant elements [18]. The soft errors can be countered mainly by error control coding whereas the hard faults can be countered by spare module/gate for replacements, faulty part isolation, or fault tolerant routing [10]. [10].…”

Section: Introductionmentioning

confidence: 99%

“…The soft errors can be countered mainly by error control coding whereas the hard faults can be countered by spare module/gate for replacements, faulty part isolation, or fault tolerant routing [10]. [10]. Some works, such as [19][20][21][22][23], addressed the permanent faults in the router by addressing the different components.…”

Section: Introductionmentioning

confidence: 99%

“…The flits are stored in the input buffer component and routed by routing components, which are the route computation component, virtual channel allocation component, and switch allocation component. The crossbar component is used to transfer flit to destination node physically [10]. Some works, such as [19][20][21][22][23], addressed the permanent faults in the router by addressing the different components.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Tolerating Permanent Faults in the Input Port of the Network on Chip Router

Mohammed

Flayyih

Rokhani

2019

JLPEA

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Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.

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A two‐dimensional RC network topology for fault‐tolerant design of analog circuits

Paiva

Galvão

Hadjiloucas

et al. 2022

Circuit Theory & Apps

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This paper proposes a novel one-port passive circuit topology consisting of a two-dimensional network of resistors and capacitors, which can be used as a fault-tolerant building block for analog circuit design. Through an analytical procedure, the network is shown to follow simple first-order admittance dynamics. A Monte Carlo method is employed to describe the effect of simultaneous faults (short or open circuit) in random network elements in terms of confidence bounds in the frequency-domain admittance profile. Faults in 10% of the elements resulted in only minor changes of the frequency response (up to 3.9 dB in magnitude and 12.5 ∘ in phase in 95% of the cases). An example is presented to illustrate the use of the proposed RC network in the faulttolerant design of a low-pass filter.

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A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model

Cited by 9 publications

References 48 publications

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

Tolerating Permanent Faults in the Input Port of the Network on Chip Router

A two‐dimensional RC network topology for fault‐tolerant design of analog circuits

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