A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Mitra, Sourav; Das, Debaprasad

doi:10.11591/ijeecs.v12.i3.pp941-949

Cited by 2 publications

(2 citation statements)

References 22 publications

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“…Non-scan cells are the cells which don't involve in scan mode, for this there are multiple explanations. One of the reasons is some cells and IPs are provided by third parties which intend those vendors don't want their IPs to be scanned for security purposes, and power consumption [17] in scan mode can be reduced. If timing analysis is performed for these cells they all will be reported for timing, this process will take additional time and effort to segregate results and reports.…”

Section: Primetime Flow To Generate the Dft Timing Constraintsmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints.

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Section: Primetime Flow To Generate the Dft Timing Constraintsmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

View full text Add to dashboard Cite

show abstract

“…In other words, if an outcome is not detected under such situations, i.e. if it has observable don't care (ODC) situations, then it is possible to insert transparent latches or floating gates at the required input [28]- [31].…”

Section: Techniques For Dynamic-power Optimizationmentioning

confidence: 99%

Power optimization of binary division based on FPGA

Nasser

Hashim

2021

IJEECS

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In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non-restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.

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A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Cited by 2 publications

References 22 publications

An effective way to generate the shift timing constraints and sanity checks

An effective way to generate the shift timing constraints and sanity checks

Power optimization of binary division based on FPGA

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