A comprehensive scheduler for asymmetric multicore systems

Sáez, Juan Carlos; Prieto, Manuel; Fedorova, Alexandra; Blagodurov, Sergey

doi:10.1145/1755913.1755929

Cited by 106 publications

(100 citation statements)

References 10 publications

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“…Third, they do not consider accelerating critical sections that are likely to be on the critical path, which UBA accelerates when critical sections have higher Utility of Acceleration than lagging threads. Fourth, [11] and [20] are coarse-grained O/S-based proposals and have higher scheduling and context switch overheads than our proposal, which manages execution migration in hardware.…”

Section: Accelerating Lagging Threads On Singlementioning

confidence: 95%

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Joao

Suleman

Mutlu

et al. 2013

SIGARCH Comput. Archit. News

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Asymmetric Chip Multiprocessors (ACMPs) are becoming a reality. ACMPs can speed up parallel applications if they can identify and accelerate code segments that are critical for performance. Proposals already exist for using coarsegrained thread scheduling and fine-grained bottleneck acceleration. Unfortunately, there have been no proposals offered thus far to decide which code segments to accelerate in cases where both coarse-grained thread scheduling and fine-grained bottleneck acceleration could have value. This paper proposes Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs (UBA), a cooperative software/hardware mechanism for identifying and accelerating the most likely critical code segments from a set of multithreaded applications running on an ACMP. The key idea is a new Utility of Acceleration metric that quantifies the performance benefit of accelerating a bottleneck or a thread by taking into account both the criticality and the expected speedup. UBA outperforms the best of two state-of-the-art mechanisms by 11% for single application workloads and by 7% for two-application workloads on an ACMP with 52 small cores and 3 large cores.

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Section: Accelerating Lagging Threads On Singlementioning

confidence: 95%

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Joao

Suleman

Mutlu

et al. 2013

SIGARCH Comput. Archit. News

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“…They proposed scheduling policies to allocate fast core cycles to applications with less parallelism to finish serial phases quickly. Saez et al proposed a new metric which combines the fast core speedup metric for single-threaded applications and the parallelism awareness [15]. However, parallelism-awareness may have a different effect on hypervisors, compared to native operating systems.…”

Section: H-1lmentioning

confidence: 99%

“…Depending on how efficiently an application exploits the different computing capabilities of core types, the best core type, which can maximize performance per area or watt, must be used for the application. To achieve the improved area/power efficiency of asymmetric multi-cores, operating systems must find the characteristics of threads and schedule them properly to the different types of cores [16,15,7].…”

Section: Introductionmentioning

confidence: 99%

Virtualizing performance asymmetric multi-core systems

Kwon

Kim

Maeng

et al. 2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

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Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric multi-core systems, operating systems are responsible for scheduling threads to different types of cores. However, system virtualization poses a challenge for such asymmetric multi-cores, since virtualization hides the physical heterogeneity from guest operating systems. In this paper, we explore the design space of hypervisor schedulers for asymmetric multi-cores, which do not require asymmetry-awareness from guest operating systems. The proposed scheduler characterizes the efficiency of each virtual core, and map the virtual core to the most area-efficient physical core. In addition to the overall system throughput, we consider two important aspects of virtualizing asymmetric multi-cores: performance fairness among virtual machines and performance scalability for changing availability of fast and slow cores.We have implemented an asymmetry-aware scheduler in the open-source Xen hypervisor. Using applications with various characteristics, we evaluate how effectively the proposed scheduler can improve system throughput without asymmetry-aware operating systems. The modified scheduler improves the performance of the Xen credit scheduler by as much as 40% on a 12-core system with four fast and eight slow cores. The results show that even the VMs scheduled to slow cores have relatively low performance degradations, and the scheduler provides scalable performance with increasing fast core counts.

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“…In these work, Kumar used simulation to investigated the performance benefit of exploiting heterogeneous architectures by evaluating heuristics to dynamically schedule thread workloads based on a speedup factor. This work lead to a number of other works on scheduling for the heterogeneous multicore [64,68,69,102,107]. The work by Winter et al [121] is related to the numerical optimization techniques used in this dissertation.…”

Section: Related Workmentioning

confidence: 99%

Rethinking the Architecture of Warehouse-Scale Computers

Mars

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As the worlds computation continues to move into the massive datacenter infrastructures recently coined as "warehouse-scale computers" (WSCs), developing highly efficient systems for these computing platforms is increasingly critical.The architecture of modern WSCs remain in their relative infancy. WSC architects have started with commodity off-the-shelf components including commodity processors and open source system software components, that are then stitched together to design a simple and cost effective WSC. This approach has been effective for producing systems that are functional, and that can scale the delivery of web-services as demand increases. However, efficiency has suffered, as these components have not been designed and refined with the unique characteristics of WSCs in mind. These characteristics may be critical for a highly efficient WSC design, and as such, we must rethink the architecture of modern WSCs.This dissertation argues that one such characteristic has been overlooked: the diversity in execution environments in modern WSCs. We define a given task's execution environment as the coupling of the machine configuration, and the co-running tasks simultaneously executing alongside the given task.At any given time in a WSC, we have a high degree of diversity across these execution environments. This dissertation argues that acknowledging, exploiting, and adapting to, the diversity in execution environments are crit-3 4 ical for the design of a highly efficient WSC. When ignoring this diversity, three critical design problems arise, including 1) the homogeneous assumption, where all machines and cores in a WSC are assumed to be equal and managed accordingly, 2) the rigidness of applications, where application binaries can not adapt to changes across and within execution environments, and 3) the oblivion of interference, where interference between tasks within an execution environment can not be measured or managed.This dissertation addresses each of these three design problems. First, we address the homogeneous assumption at the cluster level by redesigning the task manager in the WSC to learn which execution environments tasks prefer, and map them accordingly. Second, we address the rigidness of applications at the machine level by providing a mechanism to allow applications to adapt to their execution environment, and leverage this mechanism to solve pressing problems in WSCs. Lastly, we address the oblivion of interference at both the cluster and machine levels by providing novel metrics and techniques for measuring and managing interference to improve the utilization of WSCs.By incorporating an awareness of the diversity in execution environments in these three key design areas, we produce a WSC design that is significantly more efficient in both the performance of the applications that live in this domain, and the utilization of compute resources in the WSC. By improving efficiency for these two metrics, we effectively require a smaller WSC from some fixed workload, which has implic...

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A comprehensive scheduler for asymmetric multicore systems

Cited by 106 publications

References 10 publications

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Utility-based acceleration of multithreaded applications on asymmetric CMPs

Virtualizing performance asymmetric multi-core systems

Rethinking the Architecture of Warehouse-Scale Computers

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