A comprehensive survey of hardware-assisted security: From the edge to the cloud

Coppolino, Luigi; D’Antonio, Salvatore; Mazzeo, Giovanni; Romano, Luigi

doi:10.1016/j.iot.2019.100055

Cited by 49 publications

(16 citation statements)

References 16 publications

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“…Existing literature also includes surveys of TEE architectures (e.g., [85], [86]) as well as security properties (e.g., [87], [88]). Although these works cover TEEs across multiple processor architectures, none of them systematically catalog and analyze the various architectural design decisions underlying these TEE designs and analyze their advantages and disadvantages as we do in this paper.…”

Section: Related Workmentioning

confidence: 99%

SoK: Hardware-supported Trusted Execution Environments

Schneider¹,

Masti²,

Shinde³

et al. 2022

Preprint

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The growing complexity of modern computing platforms and the need for strong isolation protections among their software components has led to the increased adoption of Trusted Execution Environments (TEEs). While several commercial and academic TEE architectures have emerged in recent times, they remain hard to compare and contrast. More generally, existing TEEs have not been subject to a holistic systematization to understand the available design alternatives for various aspects of TEE design and their corresponding pros-and-cons.Therefore, in this work, we analyze the design of existing TEEs and systematize the mechanisms that TEEs implement to achieve their security goals, namely, verifiable launch, run-time isolation, trusted IO and secure storage. More specifically, we analyze the typical architectural building blocks underlying TEE solutions, design alternatives for each of these components and the trade-offs that they entail. We focus on hardware-assisted TEEs and cover a wide range of TEE proposals from academia and the industry. Our analysis shows that although TEEs are diverse in terms of their goals, usage models and instruction set architectures, they all share many common building blocks in terms of their design.

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Section: Related Workmentioning

confidence: 99%

SoK: Hardware-supported Trusted Execution Environments

Schneider¹,

Masti²,

Shinde³

et al. 2022

Preprint

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show abstract

“…Approaches and technologies under this type of security include hardwarebased hypervisors, such as the TPM chip, self-encrypting hard drive, unified extensible firmware interface (UEFI), virtualization technology, and AMD virtualization. Chip vendors and manufacturers are researching and developing security technologies based on various chips and firmware [32], [33]. Hardware security approaches are being used for mobile device security, beginning with the use of smart card ICs.…”

Section: A Hardware Securitymentioning

confidence: 99%

Design and Implementation of Secure Cryptographic System on Chip for Internet of Things

Lee

Kim

2022

IEEE Access

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Due to the 4th industrial revolution and the strength of the 5 th Generation (5G) era, the Internet of Things (IoT) industry is growing significantly. As a result, the number of IoT devices in various industries, such as smart cars, smart homes, and smart healthcare, and the importance of security for these devices are increasing. This study proposes a design method for a secure cryptographic system on a chip (SecSoC) that can be used in the IoT industry and presents the results of the performance and security evaluations of the implemented chipset. The experimental results demonstrated that the SecSoC is a low-power highperformance cryptographic chip that is safe from external attacks. Compared to conventional smart card integrated circuits, the proposed design includes intrusion detection circuits that can respond to external attacks. At the same time, it supports a physical unclonable function for hiding secret data and cryptographic logic for maintaining integrity and confidentiality. The SecSoC ensured a fast transfer rate up to 110 Mbps and consumed only 95.8 mW when operating at maximum frequency.

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“…The hardware function can reduce the complexity of the software part to improve platform performance. Therefore, the industry is advocating a full range of hardware-assisted security methods including trusted computing, random number generation, crypto acceleration, malware detection [164]. At the same time, the academic community has also proposed many security solutions based on these industrial hardware trust anchors.…”

Section: Hardware-assisted Security Unitsmentioning

confidence: 99%

A Survey on RISC-V Security: Hardware and Architecture

2021

Preprint

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The Internet of Things (IoT) is an ongoing technological revolution. Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA). In recent years, the free and open RISC-V ISA standard has attracted the attention of industry and academia and is becoming the mainstream. Many companies have already owned or are designing RISC-V processors. Many important operating systems and major tool chains have supported RISC-V. Data security and user privacy protection are common challenges faced by all IoT devices. In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices is not tampered with or leaked. Many RISC-V security research projects are underway, but the academic community has not yet conducted a comprehensive survey of RISC-V security solutions. The latest technology and future development direction of RICS-V security research are still unclear. In order to fill this research gap, this paper presents an in-depth survey on RISC-V security technologies. This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Specifically, we first briefly introduce the background and development status of RISC-V, and compare the RISC-V mechanisms with the most relevant Arm mechanisms, highlighting their similarities and differences. Then, we investigate the security research of RISC-V around the theme of hardware and architecture security. Our survey covers hardware and physical access security, hardware-assisted security units, ISA security extensions, memory protection, cryptographic primitives, and side-channel attack protection. Based on our survey, we predict the future research and development directions of RISC-V security. We hope that our research can inspire RISC-V researchers and developers.CCS Concepts: • Security and privacy → Embedded systems security; Cryptography.

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A comprehensive survey of hardware-assisted security: From the edge to the cloud

Cited by 49 publications

References 16 publications

SoK: Hardware-supported Trusted Execution Environments

SoK: Hardware-supported Trusted Execution Environments

Design and Implementation of Secure Cryptographic System on Chip for Internet of Things

A Survey on RISC-V Security: Hardware and Architecture

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