A Comprehensive Trade-off Analysis on the CCSDS 131.2-B-1 Extended ModCod (SCCC-X) Implementation

Bertolucci, Matteo; Falaschi, Francesco; Cassettari, Riccardo; Davalle, Daniele; Fanucci, Luca

doi:10.1109/dsd51259.2020.00030

Cited by 7 publications

(2 citation statements)

References 5 publications

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“…The proposed architecture supports self-configuration management and mitigation techniques to provide fault-tolerance. In [22], the new SCCC-X telemetry transmitter, which is an extension of the CCSDS 131.2-B-1 standard, is implemented and evaluated on RT Kintex UltraScale and RTG4, delivering more than 450 MSym/s and 250 MSym/s, respectively. Very recently, radiation-tolerant FPGA-based platforms for AI applications have been proposed.…”

Section: Related Work a Evaluation Of Space-grade Fpgasmentioning

confidence: 99%

Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks

et al. 2021

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The advent of space applications with increased computational requirements has led the space industry to consider innovative chips and avionics architectures for high-performance on-board data processing. In a relatively limited market, the European BRAVE 1 family of Field-Programmable Gate Arrays (FPGAs) offers such novel radiation-hardened solutions. Towards verification, the current work devises and applies a methodology to thoroughly assess the BRAVE FPGAs and their SW tools. The paper focuses on NG-Large, i.e., the largest FPGA of the 65nm Radiation-Hardened-By-Design (RHBD) technology of NanoXplore to date. The proposed approach comprises a number of customized steps to systematically evaluate the entire FPGA design flow. Initially, we carefully select and tune a set of high-performance Digital Signal Processing (DSP) & Computer Vision (CV) benchmarks, which were originally developed as Hardware Description Language (HDL) IPs in past projects of the European Space Agency (ESA). Subsequently, we perform exhaustive exploration of the Synthesis, Placement, and Routing stages of the SW tools, as well as testing on actual HW boards. At each step, we generate and analyze a variety of results, while we also compare them to 3rd-party solutions. The results show that NG-Large provides sufficient programmability and performance, e.g., classic CV IPs for feature detection on megapixel images can achieve a throughput of 5-10 frames per second, while the on-chip memory utilization is up to 56% better than that of 3rd-party FPGAs. As a highlight, at system-level, we successfully implement and execute an entire HW/SW algorithmic pipeline for Vision-Based Navigation (VBN) involving SpaceWire data transfers with LEON CPU & NG-Large co-processing.

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Section: Related Work a Evaluation Of Space-grade Fpgasmentioning

confidence: 99%

Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks

et al. 2021

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“…In the literature, several works have been carried out in order to achieve high throughput turbo-code decoders using different parallelism techniques. Most of the contributions concern PC-CCs [8] and few are dedicated to SCCCs decoders even though their efficient implementation is an issue for satellite telemetry systems [9]. In [10], a parallel SCCC-decoder architecture with 16 concurrent SISO decoders was proposed based on sliding windows parallelism technique [11].…”

Section: Introductionmentioning

confidence: 99%